KS-FX925R
1-25
VDD1
VDD2
INH
OSC
CLOCK
GENERATOR
COMON
DRIVER
SEGMENT DRIVER
SHIFT REGISTOR
ADDRESS
DETECTOR
VSS
VDD
DI
CL
CE
S5
S4/P4
S3/P3
S2/P2
S1/P1
S68
S67
COM1
COM2
COM3
LC75873NW (IC601) : LCD driver
1.Pin layout
3.Pin function
2.Block diagram
60 41
1 20
40
21
61
80
Pin No.
Pin name
Description
I/O
I/O
79,80
1,2,3
to 66
S1/P1 TO S4/P4
S5 to S68
COM1
COM2
COM3
Segment outouts for displaying the display data
transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-
purpose output ports under serial data control.
Common driver outputs.
The frame frequency f0 is given by :
f0 = (FOSC/384)Hz.
Oscillator connection
An oscillator circuit is formed by connecting an
external resistor and capacitor to this pin.
Serial data transfer inputs.
Connected to the controller.
CE:Chip enable
CL:Synchronization clock
DI:Transfer data
Display off control input
INH= "L"(VSS) Display forced off
Used for applying the LCD drive 2/3 bias voltage
externally. Must be connected to VDD2 when a
1/2 bias drive scheme is used.
Used for applying the LCD drive 1/3 bias voltage
externally. Must be connected to VDD1 when a
1/2 bias drive scheme is used.
Power supply connection.
Provide a voltage of between 3.0 and 6.0V.
Power supply connection. Connect to ground.
S1/P1 to S4/P4 = "L"
(These pins are forcibly set to the
segment output port function and held
at the low level.)
S5 to S68 = "L"
COM1 to COM3"L"
67
78
69
74
OSC
CE
CL
DI
76
77
78
75
INH
VDD1
VDD2
VDD
VSS
71
72
70
73
INH = "H"(HDD) Display on
However, serial data transfer is possible when
the display is forced off by this pin.
O
O
I
I
I
-
-
I
I
I
