JVC GC-QX3U, Service Manual

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1-8
1.4 IC BLOCK DIAGRAM
1.4.1 IC 1002 (CXD2497R)
18 17 16 15 10 9 8 21 13 12 14
28
27
26
25
30
3
31
32
33
6
2
37
48
34
45
38
42
47
40
46
44
39
43
41
5
4
24
23
22
20
19
35 36 1 29 7
11
PBLK
CLPDM
OBCLP
ADCLK
V
SS
5
ID
WEN
Pulse Generator
1/2
Selctor
Register
Selector
SSG
Latch
V Driver
OSCI
OSCO
CKI
CKO
MCKO
SNCSL
SSI
SCK
SEN
SSGSL
RST
TEST1
TEST2
V
DD
4
XSHP XSHD XRS V
SS
4
V
DD
1
V
DD
5
HD
VD
V
SS
1
V
SS
5
V
DD
2
RG V
SS
2
V
DD
3
H1 H2 V
SS
3
V1A
V1B
V2
V3A
V3B
V4
SUB
VH
VM
VL
Pin Descriptions
Pin No. Pin Name I/O
Description
1 V
SS
1 - GND
2 RST I System reset input terminal H: Reset released L: Reset
activated
(Should be activated at power ON, normally.)
(Schmitt trigger input/without protection diode on power
supply side)
3 SNCSL I Sync system switching control input terminal
(with pull-down resistor)
H: CKI sync L: MCKO sync
4 ID O Line identification pulse output terminal in the vertical
direction
5 WEN O Memory write timing pulse output terminal
6 SSGSL I Built-in SSG enable input terminal (with pull-down
resistor)
H: Built-in SSG is effective. L: External sync is effective.
7 V
DD
1 - 3.3V power (for common logic section)
8 V
DD
2 - 3.3V power (for RG terminal)
9 RG O Reset gate pulse output terminal for CCD
10 V
SS
2 - GND
11 V
SS
3 - GND
12 H1 O Clock output terminal for CCD horizontal register
13 H2 O Clock output terminal for CCD horizontal register
14 V
DD
3 - 3.3V to 5.0V power (for H1 and H2 terminals)
15 V
DD
4 - 3.3V power (for CDS system terminals)
16 XSHP O CCD pre-charge level sample/hold pulse output terminal
17 XSHD O CCD data level sample/hold pulse output terminal
18 XRS O Sample/hold pulse output terminal for phase matching in
analog-to-digital conversion
19 PBLK O Pulse output terminal for pulse cleaning during
horizontal and vertical blanking period
20 CLPDM O Pulse output terminal for CCD dummy signal clamping
21 V
SS
4 - GND
22 OBCLP O Pulse output terminal for CCD optical black signal
23 ADCLK O Clock output terminal for analog-to-digital conversion IC
Logical phase is adjustable with the serial interface data
24 V
SS
5 - GND
25 CKO O Inverter output terminal
26 CKI I Inverter input terminal
27 OSCO O Inverter output terminal for oscillation (If not used,
should be opened or connected to GND through a
capacitor.)
28 OSCI I Inverter input terminal for oscillation (If not used, should
be fixed to "Low".)
29 V
DD
5 - 3.3V power (for common logic section)
30 MCKO O System clock output terminal for signal processing IC
31 SSI I Serial interface data input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
32 SCK I Serial interface clock input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
33 SEN I Serial interface strobe input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
34 VD I/O Vertical sync signal input/output terminal
35 HD I/O Horizontal sync signal input/output terminal
36 V
SS
6 - GND
37 TEST1 I IC test terminal 1 with pull-down resistor (Should be
fixed to GND normally.)
38 VM - GND (for vertical drivers)
39 V2 O Clock output terminal for CCD vertical register
40 V4 O Clock output terminal for CCD vertical register
41 V1A O Clock output terminal for CCD vertical register
42 VH - 15.0V power (for vertical drivers)
43 V1B O Clock output terminal for CCD vertical register
44 V3A O Clock output terminal for CCD vertical register
45 VL - -7.5V power (for vertical drivers)
46 V3B O Clock output terminal for CCD vertical register
47 SUB O Pulse output terminal for CCD electronic shutter
48 TEST2 I IC test terminal 2 with pull-down resistor (Should be
fixed to GND normally.)