JVC GC-QX3U, Service Manual

Page: 14 / 164

1-9
Pin Descriptions
Pin No. Pin Name Description I/O
Analog (A) or
Digital (D)
1 NC No internal connection - -
2 D0 Digital output terminal (LSB) O D
3-10 D1-D8 Digital output terminals O D
11 D9 Digital output terminal (MSB) O D
12 NC No internal connection - -
13 OADCLK Latch clock output terminal for D0 to D9 O D
14 DV
SS
Digital GND (0V) - D
15 DV
DD
Power for digital 3.0V system - D
(Should be connected to AV
DD
outside the IC.)
16 ADCLK Analog-to-digital conversion clock input terminal I D
17 OBP Optical black pulse input terminal I D
18 SPBLK Black level sampling clock input terminal I D
19 SPSIG Signal level sampling clock input terminal I D
20 PBLK Pre-blanking signal input terminal I D
21 OADSW OADCLK enable input terminal I D
22 AV
SS
Analog GND (0V) - A
23 AV
DD
Power for analog 3.0V system - A
24 NC No internal connection - -
25 CDSSW Signal level sampling output terminal O A
26 CDSIN CDS input terminal I A
27 ADCIN ADC input terminal I A
28 BLKSH Black level sample/hold terminal - A
29 BLKFB Black level feedback terminal - A
30 AV
SS
Analog GND (0V) - A
31 AV
DD
Power for analog 3.0V system - A
(Should be connected to DVDD outside the IC.)
32 VRT Reference voltage terminal 3 - A
(Ceramic capacitor of 0.1µF or more should be
connected between this terminal and AVss.)
33 VRB Reference voltage terminal 2 - A
(Ceramic capacitor of 0.1µF or more should be
connected between this terminal and AVss.)
1.4.2 IC 2001 (CDS/AGL)
34 VRM Reference voltage terminal 1 - A
(Ceramic capacitor of 0.1µF or more should
be connected between this terminal and AVss.)
35 BIAS Internal bias terminal - A
(A 24-Kohm resistor should be connected
between this terminal and AVss.)
36 NC No internal connection - -
37 AV
SS
Analog GND (0V) - A
38 AV
DD
Power for analog 3.0V system - A
(Should be connected to DV
DD
outside the IC.)
39 NC No internal connection - -
40 AV
SS
Analog GND (0V) - A
41 AV
DD
Power for analog 3.0V system - A
(Should be connected to DV
DD
outside the IC.)
42 OEB Digital output enable control input terminal I D
43 CS Serial interface control input terminal I D
44 SCK Serial clock input terminal I D
45 SDATA Serial data input terminal I D
46 DV
DD
Power for digital 3.0V system - D
(Should be connected to AV
DD
outside the IC.)
47,48 DV
SS
Digital GND - D
13 16 18 19
42 OEB
11 D9
10 D8
9 D7
8 D6
7 D5
6 D4
5 D3
4 D2
3 D1
2
32
VRB
34
VRM
33
VR
T
35
BIAS
43
CS
45
S
D
ATA
44
SCK
17
29
OBP
20
PBLK
BLKFB
BLKSH
CDSIN
CDSSW
ADCIN
D0
26
25
27
21
O
ADSW
O
ADCLK
ADCLK SPBLK SPSIG AV
DD
DV
DD
AV
SS
DV
SS
28
CDS PGA
10bit
ADC
Output
Latch
circuit
TIMING
gen
DC offset
compensatory
Serial
Interface
Bias
Occurrence
41 46 40 48