Janz Tec emPC-CX+ System Reference Manual Download Page 4 | Manualshive

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ii

emPC-CX+

(

System Reference

Manual)

©

Janz Tec AG

Rev. 1.2

4.2

Personality Board Connector .............................................................................................39

4.3

Product History...................................................................................................................41

4.4

Manual History ...................................................................................................................42

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Summary of Contents for emPC-CX+

Page 1: ...r by any means for commercial use without the prior written permission of Janz Tec AG Germany All instructions information and specification contained in this manual are for reference only and remain subject to change without announcement emPC CX embedded computer system System Reference Manual Version 1 2 refers to product revision no V ...

Page 2: ...platforms_system_reference doc Pattern c users as appdata roaming microsoft templates normal dotm Created 24 09 2012 Last Update Stefan Althöfer 02 06 2015 Janz Tec AG 2014 Im Dörener Feld 8 PO Box 1906 D 33 049 Paderborn Germany Tel 49 5251 1550 0 FAX 49 5251 1550 90 email support janztec com Internet www janztec com ...

Page 3: ... 2 Internal USB 13 1 5 SATA 13 1 6 LVDS 14 1 7 Display Touch and Power Connector 15 2 FPGA expansion subsystem 16 2 1 Control Registers 17 2 1 1 Feature detection 17 2 1 2 Interrupt programming 17 2 1 3 Function Reset 18 2 1 4 Internal I 2 C bus 18 2 2 CAN Interface 19 2 2 1 CAN address space 19 2 2 2 CAN termination and LEDs 19 2 3 Serial Port Interface 20 2 3 1 Serial Port address space 20 2 4 N...

Page 4: ...ii emPC CX System Reference Manual Janz Tec AG Rev 1 2 4 2 Personality Board Connector 39 4 3 Product History 41 4 4 Manual History 42 ...

Page 5: ...ntroller I2C Protocols 33 List of Tables Table 1 Available Personality Board 10 Table 2 COM Express PCIe lane usage 12 Table 3 Internal USB connector 13 Table 4 COM Express SATA usage 13 Table 5 SATA power connector 14 Table 6 LVDS panel connector internal 14 Table 7 Display and touch and power connector internal 15 Table 8 PCI identification 16 Table 9 Local address spaces 16 Table 10 Control reg...

Page 6: ...ommon problems Important suggestions that should be followed will also be marked with this sign If numbers are specified in this manual they will be either decimal or hexadecimal We use C notation to identify hexadecimal numbers the 0x prefix If we refer to low active signal names they will suffixed by a character Register descriptions are done in the following style Word address Access width Acce...

Page 7: ...h the following alert symbols Acronyms and Abbreviations CAN Controller Area Network EMC Electromagnetic capability ESD Electrostatic discharge FLASH Electrically erasable PROM Capable of in circuit re programming with the capability of erasing considerably large blocks in contrast to EEPROM HDD Hard Disk Drive I O Input Output LED Light Emitting Diode MDIX Media Dependent Interface Crossover MII ...

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Page 9: ... CX series is available all common operating system 1 1 Features small housing size Typ 6 COM Express powered Up to 4x USB 3 0 2 additional internal USB 2 0 1x DVI I 2x 10 100 1000 Mbits Ethernet CFAST slot 9 14 34 V DC power supply fanless cooling concept with low power CPUs PCIe based expansion options Riser card connector with 2x X1 and 2x X4 link width PCIe mini card connector 2x X1 link on pe...

Page 10: ...ni Card I O Interfaces with personality board SATA0 SATA1 SATA2 GBE 2x 10 100 1000 BaseT Reset Button CFast Socket 9 34V DC Power input DC DC Power Management PCIe Riser Card Connector Display Interface Intel i210IT Power LED SATAActivity LED 4x USB 3 0 2x USB 2 0 PCIe Mini Card PCIe USB 2 0 PCIe LVDS DVI I Status LEDs Front Internal DVI VGA NvSRAM 2xPCIe I O s RS232 Transceiver Personality Module...

Page 11: ...nce Manual Introduction 1 9 Rev 1 2 Janz Tec AG 1 3 Front Connectors DVI I CFast LAN 2 LAN 1 Serial 1 Headers defined by personality module 4 x USB Power HDD Reset Power BTN Figure 2 emPC CX carrier module front connectors ...

Page 12: ...lity Board Pers Board Features BO EPC CPP00 2 x CAN isolated digital IO BO EPC CPP01 2 x CAN isolated BO EPC CPPS0 1 x CAN isolated 1 x RS232 digital IO BO EPC CPPS1 1 x CAN isolated 1 x RS232 BO EPC CPPU0 4 x RS232 USB based suitable for CX Lite Table 1 Available Personality Board ...

Page 13: ... manual 2 1 Installation and Maintenance 2 2 Installation and Maintenance DANGER The boards may only be operated with power supply systems with outputs which can be considered as SELV circuits WARNING The IO interfaces connectors of the boards are only suited to be connected to SELV circuits if not otherwise noted CAUTION Some of the boards are equipped with a Lithium battery Danger of explosion w...

Page 14: ...ertain COM Express module can usually be configured for different link configurations 1x X8 2x X4 NOTICE The riser card connector utilizes a 164 pin PCIe connector with nonstandard pin assignment DO NOT ATTEMPT to plug standard PCIe cards or riser cards INTO THIS SOCKET 1 1 1 PCI Express mini card The PCI Express mini card slot provides the PCI Express interface It is not compatible with mSATA sto...

Page 15: ...emPC CX provides 4 front panel USB Typ A connectors The front panel USB connectors always have the blue USB 3 0 colour code However USB 3 0 function is only available when supported by the COM Express module If the COM Express module does not support USB 3 0 the front panel USB connectors will function as USB 2 0 interfaces with full mechanical compatibility 1 4 2 Internal USB The emPC CX provides...

Page 16: ... LDDETECT DCCLK 4 5 GND DCDAT 6 7 BIASON 8 9 GND 10 11 TAx0 TAx0 12 13 GND TAx1 14 15 TAx1 GND 16 17 TAx2 TAx2 18 19 GND TAx3 20 21 TAx3 GND 22 23 TAxC TAxC 24 25 GND TBx0 26 27 TBx0 GND 28 29 TBx1 TBx1 30 31 GND TBx2 32 33 TBX2 GND 34 35 TBx3 TBx3 36 37 GND TBxC 38 39 TBxC GND 40 Table 6 LVDS panel connector internal All signals have tolerate LVTTL Level except LVDS signals The signals have the f...

Page 17: ... 8 9 GND VIN 10 11 GND VIN 12 13 GND VIN 14 15 USB USB 16 17 GND 5V 18 19 n c n c 20 Table 7 Display and touch and power connector internal All signals have tolerate LVTTL Level except USB signals The signals have the following functions Signal Names Sig Dir Description RxD Input Serial port receive signal for touch COM2 TxD Output Serial port transmit signal for touch COM2 RTS TBD RTS handshake f...

Page 18: ...bsystem ID emPC CX 0x2600 CFG space register 0x2E Table 8 PCI identification The FPGA PCIe interface provides access to several register spaces PCI base address register Description Size 0 Local configuration registers memory mapped 512 B 1 N A 2 CAN RS232 address space 8 kB 3 Reserved 8 kB 4 Control registers 4 kB 5 NVRAM IO port address space 1 MB Table 9 Local address spaces The actual addresse...

Page 19: ...1 CAN0 CAN 1 0 High if corresponding CAN is available COM 1 0 High if corresponding COM is available Reserved Reserved positions are zero REVISION BAR4 0x3c 32bit ro 31 9 9 8 7 2 1 0 TBD 2 1 2 Interrupt programming The FPGA generate an interrupt that is logically or ed amoung all internal interrupt sources To determine which source has generated an interrupt the Interrupt handler must read the int...

Page 20: ... 9 8 7 2 1 0 reserved COM1 COM0 Reserved CAN1 CAN0 RESET_DEASSERT BAR4 0x14 32bit wo 31 9 9 8 7 2 1 0 reserved COM1 COM0 Reserved CAN1 CAN0 2 1 4 Internal I 2 C bus The control register for the onboard I 2 C interface provides bit bang style I2C implementation CAN 1 0 COM 1 0 Writing one of the bits disables enables interrupts from the corresponding function Both registers are accessed in hot 1 te...

Page 21: ... SJA1000 BAR2 0x100 0x102 CAN controller 0 control BAR2 0x200 0x2ff CAN controller 1 registers SJA1000 BAR2 0x300 0x302 CAN controller 1 control Refer to SJA1000 manual for description of registers and operation 2 2 2 CAN termination and LEDs Besides the registers of the SJA1000 which are defined in the SJA1000 Manual there are two additional registers which control the line termination and the fr...

Page 22: ...ytes FIFO On customer request other serial port options are possible but not yet implemented The COM Express Typ 6 defined serial ports Rx TX only can be routed to the connectors Implementation depends on availability on the COM Express module Sometimes such ports are available as legacy ports sometimes as USB based ports sometimes as custom ports sometimes they are not available at all LPC based ...

Page 23: ...able 11 NVRAM address 128KByte NVRAM The NVRAM can be accessed by 8 16 and 32 bit operations read and write If NVRAM is accessed by 32 bit operations these are not atomic In case of power down it might happen that only parts of the 32 bit value are stored in the nvSRAM Also notice that the PCI interface has buffers Even if the write operation has been finished from CPU point of view it might not h...

Page 24: ...IO_OUT BAR5 0x1 byte rw 7 6 5 4 3 2 1 0 write 0 read as don t care OUT3 OUT2 OUT1 OUT0 DIGIO_IN BAR5 0x2 byte ro 7 6 5 4 3 2 1 0 read as don t care IN3 IN2 IN1 IN0 IN3 0 OUT3 0 status of the digital input line 0 input voltage 0 4V 1 input voltage 14 24V DIGIO_STATUS BAR5 0x3 byte ro 7 6 5 4 3 2 1 0 NO NO 1 Normal operation 0 Overheat condition the output port is shutting down This may result in co...

Page 25: ...108 32bit rw 31 25 24 20 19 14 14 13 12 11 1 0 Reserved SHIFT Reserved WP HOLD CS Reserved EN RESET 0 1 1 1 0 EN 1 enable SPI controller CS SPI FLASH chip select control 0 low HOLD SPI FLASH HOLD control 0 low WP SPI FLASH WP control 0 low SHIFT Data shift count N 1 bits are shifted out when SPI_TX is written Reserved Reserved positions are undefined and must not be considered Write reserved bit a...

Page 26: ...erface which is either provided by the FPGA subsystem standard emPC CX or by the COM express I2C interface emPC CX Lite A digital temperature sensor is available and can be read via the system MCU The ispPAC power sequencer which controls and monitors the internal power supplies The integrated ADC can check any of the internal voltages and might be read via the system MCU A fan controller which co...

Page 27: ...N required system starts automatically after power is applied figure 4 System control by power supply voltage VIN P BTN INT RESET P Off Vs0 Ts0 Ts0 Ts0 Hyst VS Ts1 1s Assumes VIN is above Vin0 0 5 all the time Hyst Ts3 once a shutdown has been triggerd it cannot be aborted by rising VS min 2s Ts2 Ts0 Ts0 Ts1 shutdown delayed by minimum n time Shutdown can be aborted during Ts3 figure 5 System cont...

Page 28: ... VS0 Yes 0x0C VHYST Yes 0x0D 0x0F Reserved 0x10 TIN00 Yes 0x11 TIN01 Yes 0x12 TIN11 Yes 0x13 TIN21 Yes 0x14 TS0 Yes 0x15 TS1 Yes 0x16 TS2 Yes 0x17 TS3 Yes 0x18 TS4 Yes 0x19 0x1f Reserved 0x20 TEMP 0x21 FANCON_RDWR D7 D0 Ack S A6 A0 0 Ack P P7 P0 Ack D7 D0 Ack Address Byte Pointer Byte Most Significant Data Byte Least Significant Data Byte D7 D0 Ack S A6 A0 0 Ack P P7 P0 Ack D7 D0 Ack Address Byte ...

Page 29: ... identify the PMON functionality and will be used to indicate revisions in the future Check for the value 0x0601 to match with this document CONTROL Pointer 1 16bit ro 15 0 EXB RESET Restored from EEPROM EXB If this bit is set the VS input mid contact on power connector act as an power button input If VS is 5 V typ the COM Express PWRBTN signal is asserted If this function is activated you should ...

Page 30: ...voltage input mid contact on power connector Reading is in units of 1 100 V so that register value of 0x800 2048 corresponds to 20 48 V VIN0 Pointer 8 16bit rw 15 0 VIN0 RESET Restored from EEPROM VIN0 VIN1 Pointer 9 16bit rw 15 0 VIN1 RESET Restored from EEPROM VIN1 If the power supply voltage level is below VIN1 then the system is held in reset This state can be left if input voltage level is ab...

Page 31: ...he sense voltage function The sense voltage level can be read from VS_ACTUAL regardless of the VS0 setting VHYST Pointer 12 16bit rw 15 0 VHYST RESET Restored from EEPROM VHYST This register sets the hysteresis for the power supply and sense input signals TIN11 Pointer 18 16bit rw 15 0 TIN11 RESET Restored from EEPROM TIN11 Reset delay see VIN1 TIN21 Pointer 19 16bit rw 15 0 TIN21 RESET Restored f...

Page 32: ...rned on The power supply is turned on and if the COM Express module does not start automatically a single power button event is generated to force turn on TS3 Pointer 22 16bit rw 15 0 TS3 RESET Restored from EEPROM TS3 A system shutdown is inhibited until the system is running for more than the time programmed by TS3 This can be used to prevent a shutdown during operating system bootup phase when ...

Page 33: ...ations the data can be read from this register 3 1 3 Command Codes This section lists the command codes that are accepted by the PMON firmware Undocumented command codes should not be issued CMD code Command Description 0 IDLE When read this command code indicates idle state 1 SAVE_EEP Save all parameters that are indicated as EEPROM saved into the PMON MCUs internal EEPROM This makes changes perm...

Page 34: ...e is used If not updated within a 2 second timeout the next priority temperature source will be used The last resort is the internal sensor The fan controller utilizes a simple linear temperature to PWM setpoint calculation as shown in figure 7 The T_LOW and T_HIGH parameters can be configured independently for all three temperature sources and are stored in the controllers internal EEPROM refer t...

Page 35: ...inter Register 0 RPM 1 reserved 2 FAN_FAULT 3 reserved 4 CONFIG 5 STATUS 6 DUTY CYCLE 7 MFR_ID 8 VER_ID 9 12 reserved debugging 13 PWM 14 TEMP 15 CMD 16 DATA0 17 DATA1 18 RTEMP1 19 RTEMP2 20 23 reserved S A6 A0 0 Ack P P7 P0 Ack D7 D0 Ack Address Byte Pointer Byte DataByte Ack S A6 A0 0 Ack P P7 P0 Ack D7 D0 Address Byte Pointer Byte DataByte Sr A6 A0 1 Ack Address Byte S P Ack Start Condition Sto...

Page 36: ...8 7 5 4 3 2 1 0 FFCLR RES DUTYC RSVD43 FPPR RSVD0 RESET 0x0a FFCLR Fan fault clear Write 1 to this bit to clear fan faults The bit is self resetting RES RPM and FAN_FAULT register resolution 0 RPM 50 1 RPM 25 DUTYC When set the fan speed is controlled by the duty cycle register When cleared the fan is controlled by temperature FPPR Fan pulses per rotation This register selects the fans number of p...

Page 37: ...MFR_ID This bit reads the value of 0x07 VER_ID Pointer 8 8bit ro 8 7 5 4 3 2 1 0 VER_ID VER_ID This bit reads the value of 0x09 PWM Pointer 13 8bit ro 8 7 5 4 3 2 1 0 PWM_SP PWM_SP Current PWM setpoint as calculated from temperature or set by DUTY_CYCLE register Values can be 0 100 decimal TEMP Pointer 14 8bit ro 8 7 5 4 3 2 1 0 TEMP TEMP The current value of the internal temperature sensor readou...

Page 38: ...l the fan Remote temperature 1 overrides the internal temperature sensor and remote temperature 2 overrides remote temperature 1 Temperature values have to be written in 2 s complement format and are interpreted as degrees Celsius Range 127 127 Both remote temperature registers are evaluated every 2 seconds and are cleared to 0x80 after being read A remote temperature is ignored if its value is 0x...

Page 39: ...m PWM value is forced Range 0 255 degrees Celsius 0x15 T0_HIGH For internal temperature sensor The temperature at which 100 PWM setting is forced Range 0 255 degrees Celsius 0x16 T1_LOW For remote temperate 1 RTEMP1 register The temperature at which minimum PWM value is forced Range 0 255 degrees Celsius 0x17 T1_HIGH For remote temperate 1 RTEMP1 register The temperature at which 100 PWM setting i...

Page 40: ...eed to know when you attempt to program the emPC CX system Most of the documents can be downloaded from the Internet Look for the WWW servers of the chip manufacturers 1 N A 2 Datasheet SJA 1000 Stand alone CAN controller Philips Semiconductors 1997 www nxp com 3 N A 4 The I2C BUS Specification Version 2 1 Philips Semiconductor 2000 5 Janz Tec AG homepage www janztec com ...

Page 41: ...FPGA_IO_07 34 35 FPGA_IO_06 FPGA_IO_01 36 37 FPGA_IO_02 FPGA_IO_04 38 39 FPGA_IO_12 FPGA_IO_03 40 41 GND GND 42 43 FPGA_IO_08 FPGA_IO_05 44 45 FPGA_IO_10 FPGA_IO_11 46 47 FPGA_IO_13 FPGA_IO_15 48 49 FPGA_IO_17 FPGA_IO_09 50 51 FPGA_IO_14 FPGA_IO_16 52 53 GND GND 54 55 S_TXD2 12V 56 57 S_DTR2 FPGA_IO_18 58 59 S_RTS2 FPGA_IO_19 50 61 S_RI2 FPGA_IO_20 62 63 S_RXD2 FPGA_IO_21 64 65 GND GND 66 67 S_DCD...

Page 42: ...O CMOS 3 3V Table 14 Personality board connector signal description If you want to design your personality board ask Janz Tec for support We can supply CAD data regarding the board shape and connector positions All FPGA defined I Os are defined by the FPGA design and can be re defined by a custom design FPGA_SCL and FPGA_SDA implement an I2C bus from FPGA to personality board Personality boards sh...

Page 43: ...emPC CX System Reference Manual Appendices 4 41 Rev 1 2 Janz Tec AG 4 3 Product History emPC CX Baseboard Version Release Date Name Changes ...

Page 44: ...sion Release Date Name Changes V1 0 2014 03 31 as Initial Version V1 1 2014 11 28 as Updated content refers to V1 4 of the baseboard Added section system control V1 2 2015 06 02 as Added missing images Added description of IO port registers Fixed BAR4 in NVRAM section where it should be BAR5 ...

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