4 - 40
emPC-CX+
(
System Reference
Manual)
Appendices
©
Janz Tec AG
Rev. 1.2
Signal Group
Origin
Signal Type
HDA_*
COM Express
I/O CMOS, 3.3V
PCIE_TX*/PCIE_RX*
COM Express
I/O PCIE, AC coupled
PCIE_CLK*
Baseboard
O PCIE
PCIE_RESET#
Baseboard
O CMOS, 3.3V
PCIE_WAKE#
COM Express
I CMOS, 3.3V
FPGA_*
FPGA
I/O CMOS, 3.3V
S_*
FPGA
I/O CMOS, 3.3V
CAN*_RX/TX
SJA1000 (opt. FPGA)
I/O CMOS, +VCAN
CAN*_TERM
FPGA
O CMOS, 3.3V
Table 14: Personality board connector signal description
If you want to design your personality board, ask Janz Tec for support. We can supply CAD data
regarding the board shape and connector positions.
All FPGA defined I/Os are defined by the FPGA design and can be re-defined by a custom design.
FPGA_SCL and FPGA_SDA implement an I2C bus from FPGA to personality board. Personality
boards should implement a 24LC32 style EEPROM with address 0x50 on this bus. This is intended for
module identification and other hardware dependent persistent storage (e.g. calibration data).
Summary of Contents for emPC-CX+
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