Janz Tec emPC-CX+, System Reference Manual

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emPC-CX+ ( System Reference Manual)

FPGA expansion subsystem 2 - 17
Rev. 1.2
© Janz Tec AG
2.1 Control Registers
Address Offset access Description
BAR4 + 0x00
RO INT_STAT
BAR4 + 0x04
RO INT_MASK
BAR4 + 0x08
WO INT_DISABLE
BAR4 + 0x0C
WO INT_ENABLE
BAR4 + 0x10
WO RESET_ASSERT
BAR4 + 0x14
WO RESET_DEASSERT
BAR4 + 0x18
RO RESET_STATUS
BAR4 + 0x1c
RW I2C_CONTROL
BAR4 + 0x20
RO FEATURE1
BAR4 + 0x24
RO FEATURE2
BAR4 + 0x30
RW TESTREG
BAR4 + 0x3C
RO REVISON
Table 10: Control registers
2.1.1 Feature detection
FEATURE1 BAR4 + 0x20 (32bit, ro)
31..9 9 8 7..2 1 0
reserved COM1 COM0 Reserved CAN1 CAN0
CAN[1..0] High if corresponding CAN is available
COM[1..0] High if corresponding COM is available
Reserved Reserved positions are zero
REVISION BAR4 + 0x3c (32bit, ro)
31..9 9 8 7..2 1 0
TBD
2.1.2 Interrupt programming
The FPGA generate an interrupt that is logically or’ed amoung all internal interrupt sources.
To determine which source has generated an interrupt the Interrupt handler must read the interrupt
status register:
INT_STAT BAR4 + 0x0 (32bit, ro)
31..9 9 8 7..2 1 0
reserved COM1 COM0 Reserved CAN1 CAN0
CAN[1..0] Interrupt status info. Each defined bit in this register reflects the status of
the INT# pin of the corresponding CAN. A zero will be read when an
interrupt is pending.
If a CAN interrupt request line is disabled, then the corresponding bit is