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User’s Manual

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Table 7-19. Input Capture Control/Status Register

Input Capture Control/Status Register

(ICCSR)

(Address = 0x56)

Bit(s)

Value

Description

7:2

(read)

These status bits (but not the interrupt enable bits) are cleared by the read of this
register, as is the Input Capture Interrupt.

The Input Capture 2 Start condition has not occurred.

(read)

The Input Capture 2 Start condition has occurred.

The corresponding Input Capture 2 Start interrupt is disabled.

(write)

The corresponding Input Capture 2 Start interrupt is enabled.

The Input Capture 2 Stop condition has not occurred.

(read)

The Input Capture 2 Stop condition has occurred.

The corresponding Input Capture 2 Stop interrupt is disabled.

(write)

The corresponding Input Capture 2 Stop interrupt is enabled.

The Input Capture 1 Start condition has not occurred.

(read)

The Input Capture 1 Start condition has occurred.

The corresponding Input Capture 1 Start interrupt is disabled.

(write)

The corresponding Input Capture 1 Start interrupt is enabled.

The Input Capture 1 Stop condition has not occurred.

(read)

The Input Capture 1 Stop condition has occurred.

The corresponding Input Capture 1 Stop interrupt is disabled.

(write)

The corresponding Input Capture 1 Stop interrupt is enabled.

The Input Capture 2 counter has not rolled over to all zeros.

(read)

The Input Capture 2 counter has rolled over to all zeros.

No effect on Input Capture 2 counter. This bit always reads as zero.

(write)

Reset Input Capture 2 counter to all zeros and clears the rollover latch.

The Input Capture 1 counter has not rolled over to all zeros.

(read)

The Input Capture 1 counter has rolled over to all zeros.

No effect on Input Capture 1 counter. This bit always reads as zero.

(write)

Reset Input Capture 1 counter to all zeros and clears the rollover latch.

1:0

Normal Input Capture operation.

Reserved for test. The Input Capture counter increments at both bit 0 and bit 8.
There is no carry from lower byte to higher byte.

Summary of Contents for Rabbit 2000

Page 1: ...The content and copyrights of the attached material are the property of its owner Distributed by www Jameco com 1 800 831 4242 ...

Page 2: ...Rabbit 3000 Microprocessor User s Manual 019 0108 040731 O ...

Page 3: ...000 Microprocessor User s Manual Part Number 019 0108 040731 O Printed in U S A 2002 2004 Rabbit Semiconductor All rights reserved Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice Trademarks Rabbit and Rabbit 3000 are registered trademarks of Rabbit Semiconductor Dynamic C is a registered trademark of Z World Inc ...

Page 4: ...rt 18 2 3 2 Standard BIOS 19 2 4 Dynamic C Support for the Rabbit 19 Chapter 3 Details on Rabbit Microprocessor Features 21 3 1 Processor Registers 21 3 2 Memory Mapping 23 3 2 1 Extended Code Space 26 3 2 2 Separate I and D Space Extending Data Memory 27 3 2 3 Using the Stack Segment for Data Storage 29 3 2 4 Practical Memory Considerations 30 3 3 Instruction Set Outline 32 3 3 1 Load Immediate D...

Page 5: ...iptions 62 5 4 Bus Timing 64 5 5 Description of Pins with Alternate Functions 65 5 6 DC Characteristics 68 5 7 I O Buffer Sourcing and Sinking Limit 69 Chapter 6 Rabbit Internal I O Registers 71 6 1 Default Values for all the Peripheral Control Registers 73 Chapter 7 Miscellaneous Functions 79 7 1 Processor Identification 79 7 2 Rabbit Oscillators and Clocks 80 7 3 Clock Doubler 83 7 4 Clock Spect...

Page 6: ...e Serial Data Timing 181 12 6 Clocked Serial Ports 182 12 7 Clocked Serial Timing 185 12 7 1 Clocked Serial Timing With Internal Clock 185 12 7 2 Clocked Serial Timing with External Clock 185 12 8 Synchronous Communications on Ports E and F 187 12 9 Serial Port Software Suggestions 192 12 9 1 Controlling an RS 485 Driver and Receiver 193 12 9 2 Transmitting Dummy Characters 193 12 9 3 Transmitting...

Page 7: ...atchdog Timer Support 238 Chapter 18 Other Rabbit Software 241 18 1 Power Management Support 241 18 2 Reading and Writing I O Registers 242 18 2 1 Using Assembly Language 242 18 2 2 Using Library Functions 242 18 3 Shadow Registers 243 18 3 1 Updating Shadow Registers 243 18 3 2 Interrupt While Updating Registers 243 18 3 3 Write only Registers Without Shadow Registers 244 18 4 Timer and Clock Usa...

Page 8: ...Revision Level ID Register 282 B 1 4 System User Mode 283 B 1 5 Memory Protection 284 B 1 6 Stack Protection 289 B 1 7 RAM Segment Relocation 291 B 1 8 Secondary Watchdog Timer 292 B 1 9 New Opcodes 293 B 1 10 Expanded I O Memory Addressing 295 B 1 11 External I O Improvements 296 B 1 12 Short Chip Select Timing for Writes 297 B 1 13 Pulse Width Modulator Improvements 311 B 1 14 Quadrature Decoder...

Page 9: ...Rabbit 3000 Microprocessor ...

Page 10: ... language development system Dynamic C Z World is providing the soft ware development tools for the Rabbit 3000 The Rabbit 3000 is easy to use Hardware and software interfaces are as uncluttered and are as foolproof as possible The Rabbit has outstanding computation speed for a micro processor with an 8 bit bus This is because the Z80 derived instruction set is very com pact and the timing of the ...

Page 11: ...ch as RAM and flash memory connect directly to the microprocessor with no glue logic A memory access time of 55 ns suffices to support up to a 30 MHz clock with no wait states with a 30 ns memory access time a clock speed of up to 50 MHz is possible with no wait states Most I O devices may be connected without glue logic The memory read cycle is two clocks long The write cycle is 3 clocks long A c...

Page 12: ...s that sup port SDLC A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a master processor The 8 bit slave port has six 8 bit registers 3 for each direction of communication Independent strobes and interrupts are used to control the slave port in both directions Only a Rabbit and a RAM chip are needed to construct a complete slave system if the clock and reset ...

Page 13: ... modes of operation used by other processors Processor current requirement is approximately 65 mA at 30 MHz and 3 3 V The cur rent is proportional to voltage and clock speed at 1 8 V and 3 84 MHz the current would be about 5 mA and at 1 MHz the current is reduced to about 1 mA To allow extreme low power operation there are options to reduce the duty cycle of memories when running at low clock spee...

Page 14: ...S2 CS1 CS0 OE1 OE0 WE1 WE0 PA 7 0 PB 7 0 PC 7 0 PD 7 0 PE 7 0 TXA RXA CLKA ATXA ARXA TXB RXB CLKB ATXB ARXB TXC RXC CLKC TXD RXD CLKD ADDRESS BUS 8 bits RESOUT PF 7 0 PG 7 0 Asynch Serial Synch Serial Asynch Bootstrap Synch Bootstrap Serial Port A Asynch Serial IrDA Serial Ports B C D Asynch Serial IrDA Asynch Serial Synch Serial Serial Ports E F Asynch Serial IrDA Asynch Serial HDLC SDLC HDLC SDL...

Page 15: ... used to create an intelligent peripheral or a slave processor For example protocol stacks can be off loaded to a Rabbit slave The master can be any processor The Rabbit can be cold booted so unprogrammed flash memory can be soldered in place You can write serious software be it 1 000 or 50 000 lines of C code The tools are there and they are low in cost If you know the Z80 or Z180 you know most o...

Page 16: ...1 5 mm LQFP 10 10 1 2 mm TFBGA 24 18 3 mm PQFP Spacing between package pins 0 4 mm 16 mils LQFP 0 8 mm TFBGA 0 65 mm 26 mils PQFP Separate power and ground for I O buffers EMI reduction Yes No Clock Spectrum Spreader EMI reduction Yes Rabbit 2000B and Rabbit 2000C versions Clock Modes 1x 2x 2 3 4 6 8 1x 2x 4 8 Power Down Modes Sleepy 32 kHz Ultra Sleepy 16 8 2 kHz Sleepy 32 kHz Low Power Memory Co...

Page 17: ...it 3000 Microprocessor Serial ports with support for SDLC HDLC IrDA communications 2 None Maximum asynchronous baud rate clock speed 8 clock speed 32 Input capture unit 2 None Feature Rabbit 3000 Rabbit 2000 ...

Page 18: ... This is because the price of static memory has decreased to the point that it has become the preferred choice for medium scale embedded systems The Rabbit has no support for DMA direct memory access because most of the uses for which DMA is traditionally used do not apply to embedded systems or they can be accomplished better in other ways such as fast inter rupt routines external state machines ...

Page 19: ...ondingly reduced using built in hardware resulting in low power consumption by the memories The Rabbit external bus uses 2 clocks for read cycles and 3 clocks for write cycles This has many advantages compared to a single clock design and on closer examination the advantages of the single clock system turn out to be mostly chimerical The advantages include easy design to avoid bus fights clean wri...

Page 20: ...ected to the Rabbit This includes HCT family parts operated at 5 V that have an input threshold between 0 8 and 2 V NOTE CMOS devices operated at 5 V that have a threshold at 2 5 V are not suitable for direct connection because the Rabbit outputs do not rise above VDD which cannot exceed 3 6 V and is often specified as 3 3 V Although a CMOS input with a 2 5 V threshold may switch at 3 3 V it will ...

Page 21: ...s Serial Port A has special features It can be used to cold boot the system after reset Serial Port A is the normal port that is used for software development under Dynamic C All the serial ports have a special timing mode that supports infrared data communications standards 2 2 3 System Clock The main oscillator uses an external crystal with a frequency typically in the range from 1 8 MHz to 26 M...

Page 22: ...ause an interrupt that can be used to set up the next bit to be output on the next timer pulse This feature can be used to generate precisely controlled pulses whose edges are positioned with high accuracy in time Applications include communications signaling pulse width modulation and driving stepper motors A separate pulse width modulation facility is also included in the Rabbit 3000 Figure 2 2 ...

Page 23: ...rt Figure 2 3 Slave Port Data Paths The slave Rabbit can read the same registers as I O registers When incoming data bits are written into one of the registers status bits indicate which registers have been written and an optional interrupt can be programmed to take place when the write occurs When the slave writes to one of the registers carrying data bits outward an attention line is enabled so ...

Page 24: ...ry bus is relieved of the capacitive load that would otherwise slow the memory For core modules based on the Rabbit 3000 fewer pins are required to exit the core module since the slave port and the I O bus can share the same pins and the memory bus no longer needs to exit the module to provide I O capability Because the I O bus has less activity and is slower than the memory bus it can be run furt...

Page 25: ...are recognized a start condition and a stop condition The start condition may be used to start counting and the stop condition to stop counting However the counter may also run continuously or run until a stop condition is encountered The start and stop conditions may also be used to latch the current time at the instant the condition occurs rather than actually start or stop the counter The same ...

Page 26: ... Once the phase relationship is known between the counters it is then possible to output pulses a precise time delay after an input pulse is captured provided that the time delay is great enough for the interrupt routine to processes the capture event and set up the output pulse synchronized by Timer B The minimum time delay needed is probably less than 10 microseconds if the software is done care...

Page 27: ...e I O ring The I O ring located on the 4 edges of the die holds the bonding pads and the large transistors used to create the I O buffers that drive signals to the external world The core section inside the I O ring contains the main processor and peripheral logic The clock and clock edges in the core are very fast with large transient currents that create a lot of noise that is communicated to th...

Page 28: ...down and provides basic services for software run ning on the Rabbit 2 4 Dynamic C Support for the Rabbit Dynamic C is Z World s interactive C language development system Dynamic C runs on a PC under Windows 32 bit operating systems Dynamic C provides a combined compiler editor and debugger The usual method for debugging a target system based on the Rabbit is to implement the 10 pin programming co...

Page 29: ...20 Rabbit 3000 Microprocessor ...

Page 30: ...sition in the instruction set as the Z80 R register but its function is to point to an interrupt vector table for internally generated interrupts Figure 3 1 Rabbit Registers A F H L D E B C IX IY SP PC A F H L D E B C Alternate Registers IP XPC IIR EIR F flag register layout S Z V C S sign Z zero V overflow C carry x x x x Bits marked x are read write 8 16 bit registers A 8 bit accumulator F flags...

Page 31: ...s The addressing range is expanded by means of the memory mapping hardware see Memory Mapping on page 23 and by special instructions For most embedded applications 64K of data mem ory as opposed to code memory is sufficient The Rabbit can efficiently handle a mega byte of program space The register SP points to the stack that is used for subroutine and interrupt linkage as well as general purpose ...

Page 32: ...dresses The processor except for certain LDP instructions sees only a 16 bit address space That is it sees 65536 distinctly addressable bytes that its instructions can manipulate Three segment registers are used to map this 16 bit space into a 1 megabyte space The 16 bit space is divided into four separate zones Each zone except the first or root zone has a segment register that is added to the 16...

Page 33: ...e startup code as well as other code that may happen to be stored there The data segment usage varies depending on the overall strategy for setting up memory It may be an extension of 10000 E000 D000 7000 0000 16 bit address space XPC segment stack segment data segment root segment 7 D 20 bit address space 00000 07000 07000 79 80000 0D000 80 8D000 0E000 85 93000 SEGSIZE register 10000 85 80 79 XPC...

Page 34: ...correspond to the normal control lines found on static mem ory chips chip select or CS output enable or OE and write enable or WE In order to generate these memory control signals the 20 bit address space is divided into four quad rants of 256K each A bank control register for each quadrant determines which of the chip selects and which pair of output enables and write enables if any is enabled wh...

Page 35: ...instructions mod ify both the program counter PC and the XPC register causing the XPC window to point to a different part of memory where the target of the long jump call or return is located The XPC segment is always 8K long The granularity with which the XPC segment can be positioned in memory is 4K Because the window can be slid by one half of its size it is possible to compile continuously wit...

Page 36: ...ill require at least 12K of root code This amount of data space is sufficient for many embedded applications One approach to getting more data space is to place data in RAM or in flash memory that is not mapped into the 64K space and then access this data using function calls or in assembly language using the LDP instructions that can access memory using a 20 bit address This greatly expands the d...

Page 37: ... into a single root code segment In the D space the segments are separately mapped to flash and RAM to provide storage for con stant data and variable data The hardware method to achieve separate 20 bit addresses for the D space is to invert either A16 or A19 for data accesses The inversion may be speci fied separately for the root segment and the data segment Normally A16 is inverted for data acc...

Page 38: ... accessed one at a time rather than randomly between all the groupings An example would be the software structures associated with a TCP IP communication protocol connection where the same code accesses the data structures associated with each connection in a pat tern determined by the traffic on each connection The advantage of this approach is that normal C data access techniques such as 16 bit ...

Page 39: ... chip interfaced using CS1 Typical Rabbit based systems use 256K of flash and 128 K of RAM but smaller or larger memories may be used Although the Rabbit can support code size approaching a megabyte it is anticipated that the majority of applications will use less than 250K of code equivalent to approximately 10 000 20 000 C statements This reflects both the compact nature of Rabbit code and the t...

Page 40: ... address space it is easy to use available RAM memory to support a large number of stacks When a pre emptive change of context takes place the STACKSEG register can be changed to map the stack segment to the portion of RAM memory that contains the stack associated with the new task that is to be run Normally the stack segment is 4K which is typically large enough to provide space for several typic...

Page 41: ...ocks for each byte of the op code and for each data byte read Three clocks are needed for each data byte written One additional clock is required if a memory address needs to be computed or an index register is used for addressing Only a few instructions don t follow this pattern An example is mul a 16 x 16 bit signed two s complement multiply mul is a 1 byte op code but requires 12 clocks to exec...

Page 42: ...ad Immediate Data to a Register A constant that follows the op code in the instruction stream can generally be loaded to any register except PC IP and F Load to the PC is a jump instruction This includes the alternate registers on the Rabbit but not on the Z180 Some example instructions appear below LD A 3 LD HL 456 LD BC 3567 not possible on Z180 LD H 0x4A not possible on Z180 LD IX 1234 LD C 54 ...

Page 43: ...egisters above or an immediate data byte LD HL r not a legal instruction LD r IX d r is any of 7 registers d is 128 to 127 offset LD r IX d same but alternate destination LD IX d r r is any of 7 registers or an immediate data byte LD IY d r IX or IY can have offset d The following are 16 bit indexed loads and stores None of these instructions exists on the Z180 or Z80 The only source for a store i...

Page 44: ... any of HL DE BC 2 bytes 4 clocks LD dd DE LD IX HL LD IY HL LD HL IY LD HL IX LD SP HL 1 byte 2 clocks LD SP IX LD SP IY Other 16 bit register moves can be constructed by using 2 byte moves 3 3 5 Register Exchanges Exchange instructions are very powerful because two or more moves are accomplished with one instruction The following register exchange instructions are implemented EX af af exchange a...

Page 45: ...ere ww is HL DE BC SP ADC HL ww ADD and ADD carry SBC HL ww sub and sub carry INC ww increment the register without affecting flags In the above op codes IX or IY can be substituted for HL The ADD and ADC instructions can be used to left shift HL with the carry An alternate destination prefix ALTD may be used on the above instructions This causes the result and its flags to be stored in the corre ...

Page 46: ... HL SBC HL HL sets HL 0 if C 0 sets HL 0ffffh if C 1 BOOL HL HL 1 if C was set otherwise HL 0 convert not carry bit into boolean variable in HL SBC HL HL HL 0 if C 0 else HL ffff if C 1 INC HL HL 1 if C 0 else HL 0 if C 1 note carry flag set but zero sign flags reversed In order to compare signed numbers using the SBC instruction the programmer can map the numbers into an equivalent set of unsigne...

Page 47: ...L LD DE n2 LD A b save sign of BC MUL form product in HL BC OR a test sign of BC multiplier JR p x1 if plus continue ADD HL DE adjust for negative sign in BC x1 RL DE test sign of DE JR nc x2 if not negative subtract other multiplier from HL EX DE HL ADD HL DE x2 final unsigned 32 bit result in HL BC This method can be modified to multiply a signed number by an unsigned number In that case only th...

Page 48: ...O address specified by the 16 bit memory address used For example IOI LD A 0x85 loads A register with contents of internal I O register at location 0x85 LD IY 0x4000 IOE LD HL IY 5 get word from external I O location 0x4005 By using the prefix approach all the 16 bit memory access instructions are available for reading and writing I O locations The memory mapping is bypassed when I O operations ar...

Page 49: ...E HL 2 EXX 2 EX DE HL 2 Move between IX IY and DE DE IX IY DE DE IX IY IX IX DE EX DE HL LD HL IX IY LD IX IY HL EX DE HL 8 clocks total DE IX IY EX DE HL LD IX IY HL EX DE HL 8 clocks total 3 4 3 Manipulation of Boolean Variables Logical operations involving HL when HL is a logical variable with a value of 1 or 0 this is important for the C language where the least bit of a 16 bit integer is used...

Page 50: ... these operations can be performed as follows assuming that the object is to set HL to 1 or 0 depending on whether the compare is true or false compute HL DE unsigned integers EX DE HL uncomment for DE HL OR a clear carry SBC HL DE C set if HL DE SBC HL HL HL HL C 1 if carry set BOOL HL set to 1 if carry else zero else result 0 unsigned integers compute HL DE or DE HL check for C EX DE HL uncommen...

Page 51: ...ero if B 0 always false LD DE 65536 B ADD HL DE not carry if HL B SBC HL HL 1 if carry else 0 INC HL 14 clocks 0 if carry else 1 if no carry HL B B is constant not zero LD DE 65535 B ADD HL DE C if HL B CCF C if true SBC HL HL if C 1 else 0 INC HL 16 clocks 1 if true else 0 HL B B is zero true if HL 0 BOOL HL result in HL HL B and B is a constant not zero LD DE 65536 B ADD HL DE zero if equal BOOL...

Page 52: ...HL 5 else false Figure 3 8 Mapping Signed Integers to Unsigned Integers by Inverting Bit 15 3 4 5 Atomic Moves from Memory to I O Space To avoid disabling interrupts while copying a shadow register to its target register it is desirable to have an atomic move from memory to I O space This can be done using LDD or LDI instructions LD HL sh_PDDDR point to shadow register LD DE PDDDR set DE to point ...

Page 53: ...e routine address for RST interrupts Since interrupt routines do not affect the XPC interrupt routines must be located in the root code space However they can jump to the extended code space after saving the XPC on the stack 3 5 1 Interrupt Priority The Z80 and Z180 have two levels of interrupt priority maskable and nonmaskable The nonmaskable interrupt cannot be disabled and has a fixed interrupt...

Page 54: ...level 1 except in carefully considered situations The effect of the processor priority on interrupts is shown in Table 3 1 The priority of the interrupt is usually established by bits in an I O control register associated with the hard ware that creates the interrupt The 8 bit interrupt register IP holds the processor priority in the least significant 2 bits When an interrupt takes place the IP re...

Page 55: ...request lines for the separate devices before they are or ed together The interrupt dis patcher calls the interrupt routines for all devices requesting interrupts in priority order so that all interrupts are serviced 3 5 3 Privileged Instructions Critical Sections and Semaphores Normally an interrupt happens at the end of the instruction currently executing However if the instruction executing is ...

Page 56: ... not have an embed ded critical section If this code is nested there is the danger of overflowing the IP register A different version that can be nested is the following PUSH IP IPSET 1 save previous priority and set priority to 1 critical section POP IP restore previous priority The following instructions are also privileged LD A xpc LD xpc a BIT B HL 3 5 5 Semaphores Using Bit B HL The bit B HL ...

Page 57: ...pc a JP HL In this case A has the new XPC and HL has the new PC This code should normally be executed in the root segment so as not to pull the memory out from under the JP HL instruction A call to a computed address can be performed by the following code A xpc IY address LD A newxpc LD IY newaddress LCALL DOCALL call utility routine in the root The DOCALL routine DOCALL LD xpc a SET xpc JP IY go ...

Page 58: ...he priority of the interrupt and the amount of time that other interrupt routines of the same or higher priority inhibit interrupts The first instruc tion of the interrupt routine will start executing within 30 clocks of the interrupt request for the highest priority interrupt routine This includes 19 clocks for the longest instruction to complete execution and 10 clocks for the interrupt to execu...

Page 59: ...er in the range of 1 256 Timer B can count as fast as 10 MHz with a 20 MHz system clock allowing events to be separated by as little as 100 ns Timer B and the match registers have 10 bits Using Timer B output pulses can be positioned to an accuracy of clk 2 Timer B can also be used to capture the time at which an external event takes place in conjunction with the external interrupt line The interr...

Page 60: ...igure 4 2 A row is driven low then the col umns are scanned for a low input line which indicates a key is closed This is repeated for each row The advantage of using open drain outputs is that if two keys in the same col umn are depressed there will not be a fight between a driver driving the line high and another driver driving it low Figure 4 2 Using Open Drain Outputs for Key Scan o d o d ...

Page 61: ...te to either memory or to internal I O space The high bit of the address is set to specify the I O space and thus writes are limited to the first 32K of either space The cold boot is terminated by a store to an address in I O space which causes execution to begin at address zero Since any memory chip can be remapped to address zero by storing in the I O space RAM can be temporarily be mapped to ze...

Page 62: ...also can do a write to the status register which is used as a signaling device and does not actually write to the status register The three registers that the master can write appear as read reg isters to the slave Rabbit The master provides an enable strobe to read the three read data registers and the status register These registers are write registers to the Rabbit The first register or the thr...

Page 63: ...n interrupt driven trans fer will be on the order of 100 clocks per byte transferred assuming a 20 instruction inter rupt routine To keep the interrupt routine to 20 instructions the interrupt routine needs to be very focused as opposed to general purpose Several methods are available to cater to a faster transfer with less computing overhead There are enough registers to transfer two bytes on eac...

Page 64: ...User s Manual 55 5 PIN ASSIGNMENTS AND FUNCTIONS ...

Page 65: ...15 A12 VDDIO VSSIO A7 A6 A5 A4 PC0 TXD PC1 RXD VSSCORE VDDCORE PC2 TXC PC3 RXC PC4 TXB PC5 RXB PC6 TXA PC7 RXA VDDIO VSSIO PF7 AQD2A PWM3 PF6 AQD2B PWM2 PF5 AQD1A PWM1 PF4 AQD1B PWM0 PB7 IA5 SLAVEATTN PB6 IA4 PB5 IA3 SA1 PB4 IA2 SA0 PB3 IA1 SRD PB2 IA0 SWR PB1 CLKA PB0 CLKB VDDIO XTALA2 XTALA1 VSSIO PA7 ID7 SD7 PA6 ID6 SD6 PA5 ID5 SD5 PA4 ID4 SD4 PA3 ID3 SD3 PA2 ID2 SD2 PA1 ID1 SD1 PA0 ID0 SD0 PF3...

Page 66: ...s of the Rabbit 3000 LQFP package Figure 5 2 Mechanical Dimensions Rabbit LQFP Package 14 00 0 10 mm 16 00 0 25 mm 0 10 mm 0 15 mm 0 60 0 18 0 05 mm 0 40 mm 14 00 0 10 mm 16 00 0 25 mm 1 00 mm The same pin dimensions apply along the x axis and the y axis 33 64 65 96 97 128 1 32 1 40 0 05 mm 0 10 0 05 mm ...

Page 67: ...Figure 5 3 PC Board Land Pattern for Rabbit 3000 128 pin LQFP 13 75 mm min 16 85 mm max 12 4 mm 15 3 mm 0 28 mm max 0 40 mm 13 75 mm min 16 85 mm max 12 4 mm 15 3 mm 1 55 mm JT 0 29 0 55 mm Toe Fillet JH 0 29 0 604 mm Heel Fillet JS 0 01 0 077 mm Side Fillet TOLERANCE AND SOLDER JOINT ANALYSIS Zmax 16 85 mm Gmin 13 75 mm X 0 28 mm Wmin Smax Lmin T Solder fillet min max toe heel and side respective...

Page 68: ...K CS2 PF6 PF4 PB5 PB1 XTALA1 PA5 PA1 PF2 WE1 A19 STATUS OE0 A10 PB7 PB4 PB0 VSSIO PA4 PA0 VDDIO VSSIO OE1 CS0 VDDCORE VSSCORE D7 PB3 VDDIO PA7 PA3 A11 A9 A8 A13 D6 D5 D4 D3 A17 VDDCORE VSSCORE A14 D2 VSSIO VDDIO D1 WE0 A18 A16 A15 A7 VSSIO VDDIO A12 A2 A1 A0 D0 A3 VDDCORE VSSCORE PE7 A6 A5 A4 PC0 VDDCORE VSSCORE PC1 PD0 PD4 VBAT CS1 WDTOUT PE3 PE4 PE5 PE6 PE2 VSSIO IOWR SMODE1 VSSIO PD7 PD3 PG3 PG...

Page 69: ...e Variation mm Ball Pitch mm Nominal Land Diameter mm Land Variation mm 0 3 0 35 0 25 0 8 0 25 0 25 0 20 Table 5 3 Design Considerations all dimensions in mm Key Feature Recommendation A Solder Land Diameter 0 254 0 010 B NSMD Defined Land Diameter 0 406 0 016 C Land to Mask Clearance min 0 050 0 002 D Conductor Width max 0 127 0 005 E Conductor Spacing typ 0 127 0 005 F Via Capture Pad max 0 406 ...

Page 70: ...kage Outline A B C D E F G H J K L M 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M 12 11 10 9 8 7 6 5 4 3 2 1 0 80 10 00 0 05 0 80 10 00 0 05 0 20 0 30 1 20 max Ball Pitch Ball Diameter 0 80 mm 0 3 mm 0 25 0 35 TOP VIEW BOTTOM VIEW ...

Page 71: ...ternal oscillator circuits 113 B7 XTALA2 Output Main Oscillator Out 114 A7 CPU Buses ADDR 19 0 Output Address Bus various DATA 7 0 Bidirectional Data Bus 10 15 18 19 D4 E1 E4 F1 F4 G0 Status Control WDTOUT Output WDT Time Out 43 J5 STATUS Output Instruction Fetch First Byte 4 C1 SMODE 1 0 Input Bootstrap Mode Select 44 45 K5 L5 Memory Chip Selects CS0 Output Memory Chip Select 0 7 D1 CS1 Output Me...

Page 72: ...ut I O Port F 127 124 103 100 A3 B3 A4 B4 A10 B10 A11 A12 PG 7 0 Input Output I O Port G 36 38 60 63 M1 M2 L3 M3 K9 L9 M9 K10 Power processor core VDDCORE 3 3 V 8 24 72 88 D2 E11 H2 J12 Power Processor I O Ring VDDIO 3 3 V 1 17 33 65 81 97 115 A1 C10 D6 F3 G10 K3 M10 Power Battery Backup VBAT 3 3 V or battery 51 J7 Ground Processor Core VSSCORE Ground 9 25 73 89 D3 E10 H3 J11 Ground Processor I O ...

Page 73: ...tually accessed Output enable and write enable are always delayed by one clock from the time the final stable address and chip select are enabled Normally the false memory access attempts to start another instruction access cycle which is aborted after one clock when the processor realizes that a read data or write data bus cycle is needed The user should not attempt a design that uses the chip se...

Page 74: ...ID 7 0 PB7 SLAVEATTN IA5 PB6 IA4 ASCS PB5 IA3 SD1 PB4 IA2 SD0 PB3 IA1 SRD PB2 IA0 SWR PB1 CLKA CLKA PB0 CLKB CLKB PC7 n a RXA yes PC6 TXA n a PC5 n a RXB yes PC4 TXB n a PC3 n a RXC yes PC2 TXC n a PC1 n a RXD yes PC0 TXD n a PD7 APWM3 ARXA yes PD6 ATXA PD5 APWM2 ARXB yes PD4 ATXB PD3 yes PD2 PD1 yes PD0 PE7 I7 SCS slave chip select PE6 I6 PE5 I5 INT1B PE4 I4 INT0B PE3 I3 PE2 I2 PE1 I1 INT1A PE0 I...

Page 75: ...1 CLKC QD1A CLKC yes PF0 CLKD QD1B CLKD PG7 APWM1 RXE yes PG6 TXE PG5 RCLKE RCLKE ARXE yes PG4 TCLKE TCLKE ARCLKE PG3 APWM0 RXF PG2 TXF PG1 RCLKF RCLKF ARXF PG0 TCLKF TCLKF ARCLKF Introduced with Rabbit 3000A chip Table 5 2 Pins With Alternate Functions continued Pin Name Output Function Input Function Input Capture Option ...

Page 76: ... corresponding port bit carries its alternate signal as an output See Table 5 4 below Only the bits that have alternate functions listed in Table 5 4 actually have a control bit in these registers That is there are four in Port C four in Port D eight in Port E four in Port F and eight in Port G Table 5 4 Parallel Port x Alternate Functions Control Bits Alternate Output Function Bit Port B Port C P...

Page 77: ...gs Symbol Parameter Maximum Rating TA Operating Temperature 55 to 85 C TS Storage Temperature 65 to 150 C Maximum Input Voltage Oscillator Buffer Input 5 V tolerant I O VDD 0 5 V 5 5 V VDD Maximum Operating Voltage 3 6 V Table 5 6 3 3 Volt DC Characteristics Symbol Parameter Test Conditions Min Typ Max Units VDD Supply Voltage 3 0 3 3 3 6 V VIH High Level Input Voltage 2 0 V VIL Low Level Input Vo...

Page 78: ...king Limit Unless otherwise specified the Rabbit I O buffers are capable of sourcing and sinking 6 8 mA of current per pin at full AC switching speeds The limits are related to the maxi mum sustained current permitted by the metallization on the die ...

Page 79: ...70 Rabbit 3000 Microprocessor ...

Page 80: ...User s Manual 71 6 RABBIT INTERNAL I O REGISTERS ...

Page 81: ... Parallel Port E No interrupts External I O Control No interrupts Pulse Width Modulator No interrupts Quadrature Decoder IIR 7 1 1 0x90 External Interrupts INT0 EIR 0x00 INT1 EIR 0x10 Timer A IIR 7 1 0 0xA0 Timer B IIR 7 1 0 0xB0 Serial Port A async cks IIR 7 1 0 0xC0 Serial Port E async hdlc IIR 7 1 1 0xC0 Serial Port B async cks IIR 7 1 0 0xD0 Serial Port F async hdlc IIR 7 1 1 0xD0 Serial Port ...

Page 82: ...ister GCDR 0x0F W 00000000 MMU Instruction Data Register MMIDR 0x10 R W 00000000 MMU Common Base Register STACKSEG 0x11 R W 00000000 MMU Bank Base Register DATASEG 0x12 R W 00000000 MMU Common Bank Area Register SEGSIZE 0x13 R W 11111111 Memory Bank 0 Control Register MB0CR 0x14 W 00001000 Memory Bank 1 Control Register MB1CR 0x15 W xxxxxxxx Memory Bank 2 Control Register MB2CR 0x16 W xxxxxxxx Mem...

Page 83: ...t 2 Register PDB2R 0x6A W xxxxxxxx Port D Bit 3 Register PDB3R 0x6B W xxxxxxxx Port D Bit 4 Register PDB4R 0x6C W xxxxxxxx Port D Bit 5 Register PDB5R 0x6D W xxxxxxxx Port D Bit 6 Register PDB6R 0x6E W xxxxxxxx Port D Bit 7 Register PDB7R 0x6F W xxxxxxxx Port E Data Register PEDR 0x70 R W xxxxxxxx Port E Control Register PECR 0x74 W xx00xx00 Port E Function Register PEFR 0x75 W 00000000 Port E Dat...

Page 84: ...00 Input Capture Source 1 Register ICS1R 0x59 W xxxxxxxx Input Capture LSB 1 Register ICL1R 0x5A R xxxxxxxx Input Capture MSB 1 Register ICM1R 0x5B R xxxxxxxx Input Capture Trigger 2 Register ICT2R 0x5C W 00000000 Input Capture Source 2 Register ICS2R 0x5D W xxxxxxxx Input Capture LSB 2 Register ICL2R 0x5E R xxxxxxxx Input Capture MSB 2 Register ICM2R 0x5F R xxxxxxxx I O Bank 0 Control Register IB...

Page 85: ... 0x02 R W xxxxxxxx Real Time Clock Byte 1 Register RTC1R 0x03 R xxxxxxxx Real Time Clock Byte 2 Register RTC2R 0x04 R xxxxxxxx Real Time Clock Byte 3 Register RTC3R 0x05 R xxxxxxxx Real Time Clock Byte 4 Register RTC4R 0x06 R xxxxxxxx Real Time Clock Byte 5 Register RTC5R 0x07 R xxxxxxxx Timer A Control Status Register TACSR 0xA0 R W 00000000 Timer A Prescale Register TAPR 0xA1 W xxxxxxx1 Timer A ...

Page 86: ...l Port A Status Register SASR 0xC3 R 0xx00000 Serial Port A Control Register SACR 0xC4 W xx000000 Serial Port A Extended Register SAER 0xC5 W 00000000 Serial Port B Data Register SBDR 0xD0 R W xxxxxxxx Serial Port B Address Register SBAR 0xD1 R W xxxxxxxx Serial Port B Long Stop Register SBLR 0xD2 R W xxxxxxxx Serial Port B Status Register SBSR 0xD3 R 0xx00000 Serial Port B Control Register SBCR 0...

Page 87: ...Port E Status Register SESR 0xCB R 0xx00000 Serial Port E Control Register SECR 0xCC W xx000000 Serial Port E Extended Register SEER 0xCD W 00000000 Serial Port F Data Register SFDR 0xD8 R W xxxxxxxx Serial Port F Address Register SFAR 0xD9 R W xxxxxxxx Serial Port F Long Stop Register SFLR 0xDA R W xxxxxxxx Serial Port F Status Register SFSR 0xDB R 0xx00000 Serial Port F Control Register SFCR 0xD...

Page 88: ...on GREV The Rabbit 3000 does not contain on chip SRAM or flash memories Table 7 1 Global ROM Configuration Register Global ROM Configuration Register GROM Address 0x2C Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00000 ROM identifier for this version of t...

Page 89: ...t that modifies the clock by shortening and lengthening clock cycles The effect of this is to spread the spectral energy of the clock harmonics over a fairly wide range of frequencies This limits the peak energy of the har monics and reduces EMI that may interfere with other devices as well as reducing the readings in government mandated EMI tests The spectrum spreader has two operating modes norm...

Page 90: ...equired Figure 7 1 Clock Distribution TN235 External 32 768 kHz Oscillator Circuits provides further information on oscilla tor circuits and selecting the values of components to use in the oscillator circuit Spectrum Spreader Clock Doubler f 8 6 4 2 22 MW Rs 330 kW C1 C2 32 768 kHz CL 7 pF Rp Cin U1A U2A SN74AHC1GU04 NC7SP14 Divider f 1 2 4 8 16 XTALB2 XTALB1 1 MW 2 5 kW Watchdog Timer Real Time ...

Page 91: ...terrupt to be pending 4 2 xxx See table below for decode of this field 1 0 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Priority 3 Table 7 6 Clock Select Field of GCSR Clock Select Bits 4 2 GCSR CPU Clock Peripheral Clock Main Oscillator Power Save CS if Enabled by GPSCR 000 ...

Page 92: ...ster Global Clock Double Register GCDR Address 0x0F Bit s Value Description 7 4 xxxx Reserved 3 0 0000 The clock doubler circuit is disabled 0001 6 ns nominal low time 0010 7 ns nominal low time 0011 8 ns nominal low time 0100 9 ns nominal low time 0101 10 ns nominal low time 0110 11 ns nominal low time 0111 12 ns nominal low time 1000 13 ns nominal low time 1001 14 ns nominal low time 1010 15 ns ...

Page 93: ... voltage is reduced fur ther to 2 0 V The values increase or decrease by 1 for each 5 C increase or decrease in temperature The doubled clock is created by xor ing the delayed and inverted clock with itself If the original clock does not have a 50 50 duty cycle then alternate clocks will have a slightly different length Since the duty cycle of the built in oscillator can be as asymmetric as 52 48 ...

Page 94: ...information on the early output enable and write enable options The spectrum spreader either stretches or shrinks the low plateau of the clock by a maxi mum of 3 ns for the normal spreading and 4 5 ns for the strong spreading If the clock dou bler is used this will cause an additional asymmetry between alternate clock cycles The power consumption is proportional to the clock frequency and for this...

Page 95: ...ding has a greater effect in reducing the peak spectral strength as shown in the figure below Figure 7 3 Reduction in Peak Spectral Strength from Spectrum Spreader In the normal spectrum spreading mode the maximum shortening of the clock cycle is 3 nanoseconds at 3 3 V and 25 C In the strong spreading mode the maximum shortening of a clock cycle under the same conditions is 4 5 ns The reduction in...

Page 96: ...o the stack if an interrupt takes place immediately after an internal or an external I O instruction The chip select will be suppressed during the write cycle and the correct return address will not be stored on the stack This happens only when an inter rupt takes place immediately after an I O instruction when the short chip select option is enabled Therefore when using the short chip select opti...

Page 97: ...d should not be used 100 296 ns self timed chip selects 192 ns best case 457 ns worst case 101 234 ns self timed chip selects 151 ns best case 360 ns worst case 110 171 ns self timed chip selects 111 ns best case 264 ns worst case 111 109 ns self timed chip selects 71 ns best case 168 ns worst case 4 0 Normal Chip Select operation 1 Short Chip Select timing when dividing main oscillator by 4 6 or ...

Page 98: ...s Manual 89 Figure 7 4 Short Chip Select Memory Read Figure 7 5 Self Timed Chip Select Memory Read Cycle clock ADDR DATA T1 T2 Valid MEMOExB MEMCSxB 32 kHz ADDR DATA T1 T2 Valid Valid MEMOExB MEMCSxB 100 ns ...

Page 99: ...clock divided by 2 10 CLK pin is low 11 CLK pin is high 5 4 00 STATUS pin is active low during a first opcode byte fetch 01 STATUS pin is active low during an interrupt acknowledge 10 STATUS pin is low 11 STATUS pin is high 3 1 WDTOUTB pin is low 1 cycle minimum 2 cycles maximum of 32 kHz 0 WDTOUTB pin follows watchdog function 2 x This bit is ignored 1 0 00 BUFEN pin is active low during external...

Page 100: ...ered down This design makes battery backup possible Since the processor operates on a different clock than the RTC there is the possibility of performing a transfer to the holding registers while a carry is taking place resulting in incorrect information In order to prevent this the processor should do the clock read twice and make sure that the value is the same in both reads If the processor is ...

Page 101: ...y either 1 disable the byte increment function or 2 cancel the RTC reset command If the 0xC0 command is followed by a 0x00 command only the byte increment function will be disabled The RTC reset will still take place 0x40 Arm RTC for a reset with code 0x80 or reset and byte increment function with code 0x0C0 0x80 Resets all six bytes of the RTC counter to 0x00 if proceeded by arm command 0x40 0xC0...

Page 102: ...hit the watchdog timer or to turn off the watchdog timer The programmer should not sprinkle instructions to hit the watch dog timer throughout his program because such instructions can become part of an endless loop if the program crashes and thus disable the recovery ability given by having a watch dog The following is a suggested method for hitting the watchdog An array of bytes is set up in RAM...

Page 103: ...go wrong go into an endless loop with interrupts off Table 7 13 Watchdog Timer Test Register WDTTR adr 0x09 Bit s Value Description 7 0 0x51 Clock the least significant byte of the watchdog timer from the peripheral clock Intended for chip test and code 0x54 below only 0x52 Clock the most significant byte of the watchdog timer from the peripheral clock Intended for chip test and code 0x54 below on...

Page 104: ...CS1 pin is powered by VBAT In this case an external pull up resistor to VBAT is required on CS1 to keep the RAM deselected during power down If the exter nal RAM connected to CS1 is not powered by VBAT so that any information held within it is lost during power down no pull up resistor on CS1 is appropriate as this would add leakage through the protection diode to drain VBAT The RESOUT signal whic...

Page 105: ...0 Input Not Affected Not Affected CS0 Output High Operational CS1 Output High Z High CS2 Output High High OE0 Output High Operational OE1 Output High High WE0 Output High High WE1 Output High High BUFEN Output High High IORD Output High High IOWR Output High High PA 7 0 Input Output zzzzzzzz zzzzzzzz PB 7 0 Input Output 00zzzzzz 00zzzzzz PC 7 0 4 In 4 Out z0z1z1z1 z0z1z1z1 PD 7 0 Input Output zzzz...

Page 106: ...he table for very small interrupt routines Interrupts have priority 1 2 or 3 The processor operates at priority 0 1 2 or 3 If an inter rupt is being requested and its priority is higher than the priority of the processor the interrupt will take place after then next instruction The interrupt automatically raises the processor s priority to its own priority The old processor priority is pushed into...

Page 107: ...put Capture Read the status from the ICCSR Slave Port Rd Read the data from the SPD0R SPD1R or SPD2R Wr Write data to the SPD0R SPD1R SPD2R or write a dummy byte to the SPSR Serial Port E Rx Read the data from the SEDR or SEAR Tx Write data to the SEDR SEAR SELR or write a dummy byte to the SESR Serial Port F Rx Read the data from the SFDR or SFAR Tx Write data to the SFDR SFAR SFLR or write a dum...

Page 108: ...y simultaneously or because the interrupts are inhibited by the processor priority then there will be only one interrupt for the two edges detected The interrupt service routine can read the interrupt pins via Parallel Port E and determine which lines experienced a transition provided that the transitions are not too fast Interrupts can also be generated by setting up the matching port E bit as an...

Page 109: ...llowing code shows how the interrupt service routines can be written External interrupt Routine 0 programmed priority could be 3 int2 PUSH IP save interrupt priority IPSET 1 set to priority really desired 1 2 etc insert body of interrupt routine here OPP IP get back entry priority IPRES restore interrupted routine s priority RET return from interrupt Table 7 16 Control Registers for External Inter...

Page 110: ...tes and bytes must be transferred often enough to prevent the watchdog timer from timing out Bootstrap operation is terminated when the SMODE pins are set to zero The SMODE pins are sampled just prior to fetching the first instruction of the bootstrap program If the SMODE pins are zero instructions are fetched from normal memory starting at address 0x0000 The Slave Port Control register allows the...

Page 111: ... like NRZ data but not so much as to interfere with real NRZ data When a bootstrap is performed using Serial Port A the TXA signal is not needed since the bootstrap is a one way communication After the reset ends and the bootstrap mode begins TXA will be low reflecting its function as a parallel port output bit that is cleared by the reset This may be interpreted as a break signal by some serial c...

Page 112: ...ng this value in each quadrant To get the exact High time the Pulse Width Modulator uses the two LSBs of the pulse width register to modify the High time in each quadrant according to the table below The n 4 term is the base count formed from the eight MSBs of the pulse width register The diagram below shows a PWM output for several different width values for both modes of operation Operation in t...

Page 113: ... Register PWM0R Address 0x89 PWM1R Address 0x8B PWM2R Address 0x8D PWM3R Address 0x8F Bit s Value Description 7 0 write The most significant eight bits for the Pulse Width Modulator count are stored With a count of n the PWM output will be High for n 1 clocks out of the 1024 clocks of the PWM counter n 255 normal n 256 spread n 255 spread 256 counts 64 counts 64 counts 64 counts 64 counts 65 count...

Page 114: ...t condition and the Stop condi tion Each of these two inputs can be programmed to come from one of four bits bits 1 3 5 or 7 in Parallel Port C D F or G The two inputs can come from the same or different pins and are edge sensitive Each input can be disabled rising edge sensitive falling edge sensitive or responsive to either edge polarity Either or both inputs can generate an Input Capture interr...

Page 115: ...nt inputs for the Start and Stop condition allows time delay measurements between two signals This is the mode to use for high speed pulse measurement because only one count latch is available and it may be overwritten if the processor is not able to read the latched value quickly enough When the counter starts from a known count only the stop count is necessary to determine the pulse width In the...

Page 116: ...t Capture 1 Start interrupt is disabled write 1 The corresponding Input Capture 1 Start interrupt is enabled 4 0 The Input Capture 1 Stop condition has not occurred read 1 The Input Capture 1 Stop condition has occurred 4 0 The corresponding Input Capture 1 Stop interrupt is disabled write 1 The corresponding Input Capture 1 Stop interrupt is enabled 3 0 The Input Capture 2 counter has not rolled ...

Page 117: ...om the Start condition until the Stop condition 10 The counter runs continuously 11 The counter runs continuously until the Stop condition 5 4 00 Disable the count latching function 01 Latch the count on the Stop condition only 10 Latch the count on the Start condition only 11 Latch the count on either the Start or Stop condition 3 2 00 Ignore the starting input 01 The Start condition is the risin...

Page 118: ... Parallel Port F used for Stop condition input 11 Parallel Port G used for Stop condition input 1 0 00 Use port bit 1 for Stop condition input 01 Use port bit 3 for Stop condition input 10 Use port bit 5 for Stop condition input 11 Use port bit 7 for Stop condition input Table 7 23 Input Capture LSB x Register Input Capture LSB x Register ICL1R Address 0x5A ICL2R Address 0x5E Bit s Value Descripti...

Page 119: ...ng or exiting the disable state The operation of the counter as a function of the I and Q inputs is shown below The Quadrature decoders are clocked by the output of Timer A10 giving a maximum clock rate of one half of the peripheral clock rate The time constant of Timer A10 must be fast enough to sample the inputs properly Both the I and Q inputs go through a digital fil ter that rejects pulses sh...

Page 120: ...from 0xFF to 0x00 or when the counter decrements from 0x00 to 0xFF The timing for the interrupt is shown below Note that the status bits in the QDCSR are set coincident with the interrupt and the interrupt and status bits are cleared by reading the QDCSR Rejected Accepted Peri Clock Timer A10 ...

Page 121: ...ared by a read of this register 5 This bit always reads as zero 4 0 No effect on the Quadrature Decoder 2 write only 1 Reset Quadrature Decoder 2 to 0x00 without causing an interrupt 3 0 Quadrature Decoder 1 did not increment from 0xFF read only 1 Quadrature Decoder 1 incremented from 0xFF to 0x00 This bit is cleared by a read of this register 2 0 Quadrature Decoder 1 did not decrement from 0x00 r...

Page 122: ...er 1 inputs Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement 01 This bit combination is reserved and should not be used 10 Quadrature Decoder 1 inputs from Port F bits 1 and 0 11 Quadrature Decoder 1 inputs from Port F bits 5 and 4 1 0 00 Quadrature Decoder interrupts are disabled 01 Quadrature Decoder interrupt use Interrupt Priority 1 10 Quadrature ...

Page 123: ...114 Rabbit 3000 Microprocessor ...

Page 124: ...attery backing of static RAM When the processor power is removed but battery power is supplied to the battery power pin VBAT CS1 is held in a high impedance state This allows a pull up resistor to the bat tery backup power to hold CS1 high and thus hold the static memory chip in standby mode The RESOUT pin is also held high while the processor is powered down and bat tery power is supplied to VBAT...

Page 125: ...116 Rabbit 3000 Microprocessor Figure 8 2 Typical Memory Chip Connection Rabbit 3000 DATA LINES 8 ADDRESS LINES 20 CS WE OE CS0 CS1 CS2 OE0 OE1 WE0 WE1 STATIC CS WE OE MEMORY FLASH STATIC MEMORY RAM ...

Page 126: ...s vanish from the memory map The four segments are shown in the example in Figure 8 4 The segment size register SEGSIZE determines the boundaries marked in the diagram The extended code seg ment always occupies the addresses 0x0E000 0x0FFFF The stack segment stretches from the address specified by the upper 4 bits of the SEGSIZE register to 0x0DFFF For exam ple if the upper 4 bits of SEGSIZE are 0...

Page 127: ...create a 20 bit address Wraparound occurs if the addition would result in an address that does not fit in 20 bits Table 8 1 Segment Registers Segment Register Function XPC Locates extended code segment in physical memory Read and written by processor instructions ld a xpc ld xpc a lcall lret ljp STACKSEG 0x11 Locates stack segment in physical memory DATASEG 0x12 Locates data segment in physical me...

Page 128: ...patched to the memory chips connected to the Rabbit There are three separate chip select output lines CS0 CS1 and CS2 that can be used to select one of three different memory chips A field in the control register determines which chip select is selected for memory accesses to the quadrant The same chip select line may be accessed in more than one quadrant For example if a 512K RAM is installed and...

Page 129: ...es of 256K each There is no effect outside the quadrant that the memory bank control register is controlling Table 8 3 Memory Bank Control Register x MBxCR 0x014 x Memory Bank x Control Register MB0CR Address 0x014 MB1CR Address 0x015 MB2CR Address 0x016 MB3CR Address 0x017 Bit s Value Description 7 6 00 Four wait states for accesses in this bank 01 Two wait states for accesses in this bank 10 One...

Page 130: ...d RAM By enabling CS1 the delay time of the switch that forces CS1 high when power is off can be bypassed This feature increases power consumption since the RAM is always enabled and its access is controlled normally by OE1 Table 8 4 MMU Instruction Data Register MMIDR 0x010 See Table B 20 for information on bit 7 for Rabbit 3000A and later versions MMU Instruction Data Register MMIDR Address 0x01...

Page 131: ...A18 110 For an XPC access use MB2CR independent of A19 A18 111 For an XPC access use MB3CR independent of A19 A18 Table 8 6 Memory Timing Control Register MTCR adr 0x019 Memory Timing Control Register MTCR Address 0x019 Bit s Value Description 7 4 xxxx These bits are reserved and should not be used 3 0 Normal timing for OE1B rising edge to rising edge one clock minimum 1 Extended timing for OE1B o...

Page 132: ... low memory and compiles upward Allocation of extended code starts above the root code and data Allocation normally con tinues to the end of the flash memory Data variables are allocated to RAM working backwards in memory Allocation normally starts at 52K in the 64K D space and continues The 52K space must be shared with the root code and data and is allocated upward from zero Dynamic C also suppo...

Page 133: ...fter the quadrant has been selected The inversion of A19 or A16 controlled by the MMIDR register on D space accesses is used to separate I and D space to different memory locations The separation of I and D space can only occur for the first two memory zones in the64K space For each zone the root code segment and the data segment either or both of A19 and A16 can be inverted The reasoning behind t...

Page 134: ...s The relative size of the two parts depends on the lower 4 bits of the SEGSIZE register which define the 4K page boundary between the root segment and the data segment Figure 8 5 Combined versus Separate I D Space The use of physical memory that goes with this map is shown in Figure 8 6 Use of Phys ical Memory Separate I D Space Model on page 126 In this figure n is the number of 4k pages devoted...

Page 135: ...ess these regardless of the state of the user program The Dynamic C debugger vari ables are kept at the top of the data segment starting at 52k and working down in memory The user program variables are allocated by the compiler starting just below the Dynamic C debugger data The Dynamic C constants start at address zero User constants are allo cated stating at a low address just above the Dynamic ...

Page 136: ...with The 16 bit PC controls the address of the instruction usually in the region E000 to FFFF The advantage of paged access is that most instructions continue to use 16 bit addressing Only when an out of range transfer of control is made does a 20 bit transfer of control need to be made The beauty of having a 4K minimum step in page alignment while the size of the page is 8K is that code can be co...

Page 137: ...128 Rabbit 3000 Microprocessor ...

Page 138: ...n be clocked into the output registers under timer control for pulse generation Port F As outputs Port F can be configured as open drain outputs Alternatively Par allel Port F outputs can carry the four Pulse Width Modulator outputs As inputs Paral lel Port F inputs can carry the inputs to the two channels of the quadrature decoders Port F pins can also be configured to be used as clock pins for c...

Page 139: ...A is set up as an input port on reset When the port is read the value read reflects the voltages on the pins 1 for high and 0 for low This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage NOTE Refer to Section 9 6 1 Using Parallel Port A and Parallel Port F for more information Table 9 1 Parallel Port A Registers Regis...

Page 140: ...PB6 and PB7 this signal is on the signaling lines from the slave port logic Regardless of whether the slave port is enabled PB0 reflects the input of the pin unless Serial Port B has its internal clock enabled which causes this line to be driven by the serial port clock PB1 reflects the input of the pin unless Serial Port A has its internal clock enabled PBDR Parallel Port B data register Read Wri...

Page 141: ...icated outputs as serial port outputs When serving as serial inputs the data lines can still be read from the Parallel Port C data register The parallel port outputs can be selected to be serial port outputs by setting the corresponding bit positions in the Port C Function register PCFR When a parallel port output pin is selected to be a serial port output the value stored in the data register is ...

Page 142: ...ection register is zeroed making all pins inputs In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with port D are not initialized on reset Table 9 7 Parallel Port D Registers Register Name Mnemonic I O address R W Reset Port D Data Register PDDR 0x60 R W xxxxxxxx Port D Contr...

Page 143: ...0 Microprocessor Figure 9 1 Parallel Port D Block Diagram PD7 PD4 I O Data perclk 2 Timer A1 Timer B1 Timer B2 perclk 2 Timer A1 Timer B1 Timer B2 PD3 PD0 ATXA ATXB ARXA ARXB PD5 PD6 inputs Driver optional open drain ...

Page 144: ...ut dir out dir out dir out PDB0R W adr 0x068 x x x x x x x PD0 PDB1R W adr 0x069 x x x x x x PD1 x PDB2R W adr 0x 06A x x x x x PD2 x x PDB3R W adr 0x06B x x x x PD3 x x x PDB4R W adr 0x06C x x x PD4 x x x x PDB5R W adr 0x06D x x PD5 x x x x x PDB6R W adr 0x06E x PD6 x x x x x x PDB7R W adr 0x06F PD7 x x x x x x x Table 9 9 Parallel Port D Control Register adr 0x064 Bits 7 6 Bits 5 4 Bits 3 2 Bits...

Page 145: ...sponding pin a regular output A 1 makes the corresponding pin an open drain output Write only PDFR Parallel Port D function control register This port may be used to make port positions 4 and 6 be serial port outputs Write only PDBxR These eight registers may be used to set outputs on individual port positions PDCR Parallel Port D control register This register is used to control the clocking of t...

Page 146: ... the port E outputs can be configured as an I O strobe In addition four of the port E lines can be used as interrupt request inputs The output registers are cas caded and timer controlled making it possible to generate precise timing pulses Figure 9 2 Parallel Port E Block Diagram PE7 PE4 I O Data perclk 2 Timer A1 Timer B1 Timer B2 perclk 2 Timer A1 Timer B1 Timer B2 PE3 PE0 I6 scs Inputs I4 I7 I...

Page 147: ... are reset to zero On reset the data direction register and function register are zeroed making all pins inputs and disabling the alternate output functions In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with Port E are not initialized on reset Table 9 10 Parallel Port E Re...

Page 148: ...x x PE0 PEB1R W adr 0x079 x x x x x x PE1 x PEB2R W adr 0x07A x x x x x PE2 x x PEB3R W adr 0x07B x x x x PE3 x x x PEB4R W adr 0x07C x x x PE4 x x x x PEB5R W adr 0x07D x x PE5 x x x x x PEB6R W adr 0x07E x PE6 x x x x x x PEB7R W adr 0x07F PE7 x x x x x x x Table 9 12 Parallel Port E Control Register adr 0x074 Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 x x 00 clock upper nibble on pclk 2 01 clock on ti...

Page 149: ...ocked serial mode two pins of Parallel Port F are used to carry the serial clock signals When the internal clock is selected in these serial ports the corresponding bit of Parallel Port F is set as an output The Parallel Port F registers and their functions are described in Table 9 14 and in Table 9 15 Table 9 13 Parallel Port F Registers Register Name Mnemonic I O address R W Reset Port F Data Re...

Page 150: ...t F and Parallel Port A under certain conditions This bug has been corrected in ver sions of the Rabbit chip designated 3000A and later See Appendix B for further details The bug is rooted in an incomplete address decode for the data output register for Parallel Port A This register responds to any of 16 addresses 30 to 3F hex When Parallel Port F was added the addresses 38 to 3F were used and the...

Page 151: ...put register of Parallel Port A A simple way to resolve this is to leave Parallel Port A as an input until you complete the setup of Parallel Port F and then switch Parallel Port A to be an output You can always use pins on Parallel Port F as inputs If you enable the slave port then you cannot use Parallel Port F as parallel outputs but you can still use the other output functions of Parallel Port...

Page 152: ...nputs Port G can carry the data and clock inputs for these two serial ports The following registers are described in Table 9 17 and in Table 9 18 Table 9 16 Parallel Port G Registers Register Name Mnemonic I O address R W Reset Port G Data Register PGDR 0x48 R W xxxxxxxx Port G Control Register PGCR 0x4C W xx00xx00 Port G Function Register PGFR 0x4D W xxxxxxxx Port G Drive Control Register PGDCR 0...

Page 153: ...DCR Parallel Port G drive control register A 0 makes the corresponding pin a regular output A 1 makes the corresponding pin an open drain output Write only PGDDR Port G data direction register Set to 1 to make corresponding pin an out put This register is zeroed on reset On reset the data direction register is zeroed making all pins inputs In addition certain bits in the control register are zeroe...

Page 154: ...ait states that will be inserted in the I O bus cycle Writes can also be suppressed for any of the strobes The types of strobes are shown in Figure 10 1 Each of the eight I O strobes is active for addresses occupying 1 8th of the 64K external I O address space Figure 10 1 External I O Bus Cycles ADDR T1 Tw T2 write data write strobe read data read strobe chip select strobe valid valid valid Extern...

Page 155: ...ates for accesses in this bank 01 Seven wait states for accesses in this bank 10 Three wait states for accesses in this bank 11 One wait state for accesses in this bank 5 4 00 The Ix signal is an I O chip select 01 The Ix signal is an I O read strobe 10 The Ix signal is an I O write strobe 11 The Ix signal is an I O data read or write strobe 3 0 Writes are not allowed to this bank Transactions are...

Page 156: ...the internal I O space which does not have wait states associated with read or write access Internal I O read or write cycles are two clocks long The I O strobes greatly simplify the interfacing of external devices On reset the upper 5 bits of each register are cleared Parallel Port E will not output these signals unless the data direction register bits are set for the desired output positions In ...

Page 157: ...148 Rabbit 3000 Microprocessor ...

Page 158: ...ions but it cannot generate the baud clock Timer B is more flexible when it can be used because the program can read the time from a continu ously running counter and events can be programmed to occur at a specified future time Figure 11 1 Block Diagram of Timers A and B A1 A2 Timer A System match reg match reg compare Timer B System match preload match preload 10 bits Timer_B1 Timer_B2 A3 A4 A5 A...

Page 159: ...e on the negative edge of this pulse When the counter reaches zero the reload register is loaded on the next input pulse instead of a count being performed The reload registers may be reloaded at any time since the peripheral clock is synchronous with the processor clock Timers A2 A3 A4 A5 A6 and A7 always provide the baud clock for Serial Ports E F A B C and D respectively Except for very low bau...

Page 160: ...ake place as soon as priorities allow However if the bit is cleared before the interrupt is latched the bit will not cause an interrupt The proper rule to follow is for the interrupt routine to handle all bits that it sees set Although timers A8 A10 are part of Timer A they are dedicated to the input pulse cap ture PWM and quadrature decoder peripherals respectively The peripherals clocked by thes...

Page 161: ...rol and Status Register Timer A Control and Status Register TACSR Address 0x00A0 Bit s Value Description 7 read 0 A7 counter has not reached its terminal count 1 A7 count done This status bit is cleared by a read of this register 7 write 0 A7 interrupt disabled 1 A7 interrupt enabled 6 read 0 A6 counter has not reached its terminal count 1 A6 count done This status bit is cleared by a read of this...

Page 162: ... done This status bit is cleared by a read of this register 2 write 0 A2 interrupt disabled 1 A2 interrupt enabled 1 read 0 A1 counter has not reached its terminal count 1 A1 count done This status bit is cleared by a read of this register 1 write 0 A1 interrupt disabled 1 A1 interrupt enabled 0 write only 0 Disable Timer A main clock perclk 2 1 Enable Timer A main clock perclk 2 Table 11 3 Timer ...

Page 163: ...ut of Timer A1 5 0 Timer A5 clocked by the main Timer A clock 1 Timer A5 clocked by the output of Timer A1 4 0 Timer A4 clocked by the main Timer A clock 1 Timer A4 clocked by the output of Timer A1 3 0 Timer A3 clocked by the main Timer A clock 1 Timer A3 clocked by the output of Timer A1 2 0 Timer A2 clocked by the main Timer A clock 1 Timer A2 clocked by the output of Timer A1 1 0 00 Timer A in...

Page 164: ...ort is going to be used and a timer is needed to provide the baud clock that timer will be set up to be driven directly from the clock and the interrupt associated with that timer will be disabled Serial port interrupts are generated by the serial port logic The value in the reload register can be changed while the timer is running to change the period of the next timer cycle When the reload regis...

Page 165: ...ster is advanced to the next match register when the match pulse is generated Every time a match condition occurs the processor sets an internal bit that marks the match value in TBLxR as invalid Reading TBCSR clears the interrupt condition TBLxR must be reloaded to re enable the interrupt TBMxR does not need to be reloaded every time If both match registers need to be changed the most significant...

Page 166: ...tor has not encountered a match condition 1 Timer B1 comparator has encountered a match condition This status bit and the Timer B1 interrupt but not interrupt enable are cleared by a read of this register 1 write 0 Timer B1 interrupt disabled 1 Timer B1 interrupt enabled 0 0 Disable the main clock for Timer B 1 Enable the main clock for Timer B Table 11 8 Timer B Control Register Timer B Control R...

Page 167: ...zeroes Table 11 10 Timer B Count LSB x Registers Timer B Count LSB x Register TBL1R Address 0xB3 TBL2R Address 0xB5 Bit s Value Description 7 0 Write The eight LSBs of the comparae value for the Timer B comparator are stored This compare value will be loaded into the actual comparator when the current compare detects a match Table 11 11 Timer B Count MSB Register Timer B Count MSB Register TBCMR A...

Page 168: ...r 8 bits The following method is suggested 1 Read the lower 8 bits read TBCLR register 2 Read the upper 2 bits read TBCMR register 3 Read the lower 8 bits again read TBCLR register 4 If bit 7 changed from 1 to 0 between the first and second read of the lower 8 bits there has been a carry to the upper 2 bits In this case read the upper 2 bits again and decre ment those 2 bits to get the correct upp...

Page 169: ...errupt If the system clock is 20 MHz the counter can count as fast as 10 MHz The uncertainty in a pulse width measure ment can be nearly as low as 38 clocks 2 x 19 or about 2 µs for a 20 MHz system clock Timer B can be used to change a parallel port output register at a particular specified time in the future A pulse train with edges at arbitrary times can be generated with the restric tion that t...

Page 170: ...rial port signals Table 12 1 Serial Port Signals Serial Port Signal Name Function Serial Port A TXA Serial Transmit Out RXA Serial Transmit In CLKA Clock for clocked mode bidirectional ATXA Alternate serial transmit out ARXA Alternate serial receive in Serial Port B TXB Serial Transmit Out RXB Serial Transmit In CLKB Clock for clocked mode bidirectional ATXB Alternate serial transmit out ARXB Alte...

Page 171: ...it clock RCLKF Optional external receive clock Table 12 1 Serial Port Signals continued Serial Port Signal Name Function Serial Port A Timer A4 Serial Port B Timer A5 TXA RXA TXB RXB CLKA CLKB Input to timers perclk or perclk 2 or prescaled Timer A1 ATXA ATXB Serial Port C Timer A6 TXC RXC CLKC Serial Port D Timer A7 TXD RXD CLKD Serial Port E Timer A2 TXE RXE RCLKE TCLKE Serial Port F Timer A3 TX...

Page 172: ...8 data bits may be transmitted and received in the asynchronous mode The so called 9th bit or address bit mode of operation is also supported The 9th bit can be set high or low by accessing the appropriate serial port register Although Parity and multiple stop bits are not directly supported by the hardware the 9th bit can be used to issue an extra stop bit 9th bit high or toggled to indicate pari...

Page 173: ...om the data register LSB first The control regis ter is used to set the transmit and receive parameters The status register may be tested to check on the operation of the serial port Figure 12 2 Functional Block Diagram of a Serial Port Bit 0 1 2 3 4 5 6 7 stop Rx serial data in Tx serial data out Read Data Write Data Input Shift Reg Data In Reg Data Out Reg Start Bit 0 1 1 0 1 0 1 1 Transmitting ...

Page 174: ...mers can divide the frequency by any number from 1 to 256 see Chapter 11 The input frequency to the timers can be selected in different ways described in the documentation for the timers One choice is the peripheral clock with that choice and a well chosen crystal frequency for the main oscillator the most commonly used baud rates can be obtained down to approximately 2400 bps or lower by prescali...

Page 175: ...0xC5 W 00000000 Table 12 3 Serial Port B Registers Register Name Mnemonic I O Address R W Reset Serial Port B Data Register SBDR 0xD0 R W xxxxxxxx Serial Port B Address Register SBAR 0xD1 W xxxxxxxx Serial Port B Long Stop Register SBLR 0xD2 W xxxxxxxx Serial Port B Status Register SBSR 0xD3 R 0xx00000 Serial Port B Control Register SBCR 0xD4 W xx000000 Serial Port B Extended Register SBER 0xD5 W ...

Page 176: ... Port E Data Register SEDR 0xC8 R W xxxxxxxx Serial Port E Address Register SEAR 0xC9 W xxxxxxxx Serial Port E Long Stop Register SELR 0xCA W xxxxxxxx Serial Port E Status Register SESR 0xCB R 0xx00000 Serial Port E Control Register SECR 0xCC W xx000000 Serial Port E Extended Register SEER 0xCD W 000x000x Table 12 7 Serial Port F Registers Register Name Mnemonic I O Address R W Reset Serial Port F...

Page 177: ... Description 7 0 Read Returns the contents of the receive buffer In Clocked Serial mode reading the data from this register automatically causes the receiver to start a byte receive operation the current contents of the receive buffer are read first eliminating the need for software to issue the Start Receive command Write Loads the transmit buffer with an address byte marked with a zero address b...

Page 178: ...E2 SDLR Address 0xF2 SELR Address 0xCA SFLR Address 0xDA Bit s Value Description 7 0 Read Returns the contents of the receive buffer Write Loads the transmit buffer with an address byte marked with a one address bit for transmission In HDLC mode the last byte of a frame is written to this register to enable subsequent closing Flag transmission ...

Page 179: ...receive buffer was not overrun 1 This bit is set if the receiver is overrun This happens if the shift register and the data register are full and a start bit is detected This bit is cleared when the receiver data register is read 4 0 This bit is always zero in async mode 3 0 The transmit buffer is empty 1 Transmitter data buffer full This bit is set when the transmit data register is full that is ...

Page 180: ...he receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 This bit is always zero in clocked serial mode 3 0 The transmit buffer is empty 1 The transmit buffer is not empty The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer Transmit interrupts are cleared when the transmit buffer is written or any value which will be ignor...

Page 181: ...uffer is empty 1 The transmit buffer is not empty The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer unless the byte is marked as the last in the frame Transmit interrupts are cleared when the transmit buffer is written or any value which will be ignored is written to this register 2 1 00 Transmit interrupt due to buffer empty condition 01 Transmit...

Page 182: ...used for input 01 Parallel Port D is used for input 1x Disable the receiver input 3 2 00 Async mode with 8 bits per character 01 Async mode with 7 bits per character In this mode the most significant bit of a byte is ignored for transmit and is always zero in receive data 10 Clocked serial mode with external clock Serial Port A clock is on Parallel Port PB1 Serial Port B clock is on Parallel Port ...

Page 183: ...e receiver input 1 Disable the receiver input 4 x This bit is ignored 3 2 00 8 bits per character 01 7 bits per character In this mode the most significant bit of a byte is ignored for transmit and is always zero in receive data 10 Clocked serial mode with external clock Serial Port C clock is on Parallel Port PF1 Serial Port D clock is on Parallel Port PF0 11 Clocked serial mode with internal clo...

Page 184: ...f a byte is ignored for transmit and is always zero in receive data 10 HDLC mode with external clock The external clocks are supplied as follows Transmit clock Serial Port F pins PG0 and PG1on Parallel Port G Receive clock Serial Port E pins PG4 and PG5 on Parallel Port G 11 HDLC mode with internal clock The clock is 16 the data rate and the DPLL is used to recover the receive clock If necessary t...

Page 185: ... xxx These bits are ignored in async mode 4 0 Normal async data encoding 1 Enable RZI coding 3 16ths bit cell IrDA compliant 3 0 Normal Break operation This option should be selected when address bits are expected 1 Fast Break termination At the end of Break a dummy character is written to the buffer and the receiver can start character assembly after one bit time 2 0 Async clock is 16X data rate ...

Page 186: ... synchronized clocked serial uses Timer B2 5 4 00 Normal clocked serial clock polarity inactive High Internal or external clock 01 Normal clocked serial clock polarity inactive Low Internal clock only 10 Inverted clocked serial clock polarity inactive Low Internal or external clock 11 Inverted clocked serial clock polarity inactive High Internal clock only 3 2 xx These bits are ignored in clocked ...

Page 187: ...iphase Level Manchester data encoding for HDLC receiver and transmitter 110 Biphase Space data encoding for HDLC receiver and transmitter 111 Biphase Mark data encoding for HDLC receiver and transmitter 4 0 Normal HDLC data encoding 1 Enable RZI coding 1 4th bit cell IRDA compliant This mode can only be used with internal clock and NRZ data encoding 3 0 Idle line condition is Flags 1 Idle line con...

Page 188: ...ure 12 3 Generation of Serial Port Interrupts The receive interrupt request flip flop is set after the stop bit is sampled on receive nomi nally 1 2 of the way through the stop bit Data bits are transferred on this same clock from the receive shift register to the receive data register The transmit interrupt request flip flop is set on the leading edge of the start bit for data register empty and ...

Page 189: ...data register empty This causes an interrupt request The interrupt routine normally answers the interrupt before the shift register runs dry 9 to 11 baud clocks depending on the mode of operation The interrupt routine stores the next data item in the data register clearing the interrupt request and supplying the next data bits to be sent When all the characters have been sent the interrupt service...

Page 190: ...pt if enabled is requested On receive an interrupt is requested when the receiver data register has data This hap pens when data bits are transferred from the receive shift register to the data register This also sets bit 7 of the status register The interrupt request and bit 7 are cleared when the data register is read An interrupt is requested if bit 7 is high The interrupt is requested on the e...

Page 191: ...ullup resistor is needed on the clock line to prevent spurious clocks while neither party is driving the clock Figure 12 5 Clock Polarities Supported in Clocked Serial Mode In clocked serial mode the shift register and the data register work in the same fashion as for asynchronous communications However to initiate basic sending or receiving a command must be issued by writing to bits 7 6 of the c...

Page 192: ...ceive will be initiated without pausing the clock To do this the interrupt has to be ser viced within 1 2 clock To transmit each byte in external clock mode the user must load the data register and then store the send code When the shift register is idle and the receiver provides a clock burst the data bits are transferred to the shift register and are shifted out Once the transfer is made to the ...

Page 193: ...s the data rate slows to 40 000 bytes per second If it can answer in 3 5 clocks or 8 75 µs the data rate will slow to 36 363 bytes per second and so forth If two way half duplex communication is desired the clock can be turned around so that the receiver always provides the clock This is slightly more complicated since the receiver cannot initiate a message If the receiver attempts to receive a ch...

Page 194: ...7 2 Clocked Serial Timing with External Clock In a system where the Rabbit serial clock is generated by an external device the clock sig nal has to be synchronized with the internal peripheral clock perclk before data can be transmitted or received by the Rabbit Depending on when the external serial clock is gen erated in relation to perclk it may take anywhere from 2 to 3 clock cycles for the ext...

Page 195: ... with External Clock Mode 00 When clocking the Rabbit externally the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit perclk If we sum the maximum number of perclk cycles required to perform clock synchroniza tion for each of the receive and transmit cases then the fastest external serial clock fre quency would be limited to...

Page 196: ...ritten to the address register or long stop register Writing to the address register appends an zero address bit to the data while writing to the long stop register appends an one address bit to the data The address bit is followed by a normal stop bit Normal data is written to the data register to be transmitted On receive a status bit distinguishes normal data from address data This status bit i...

Page 197: ...ring for the data Status bits are buffered along with the data in both receiver and transmitter The receiver automati cally generates an interrupt at the end of a received frame and the transmitter generates an interrupt at the end of CRC transmission at the end of the transmission of an Abort sequence and at the end of the transmission of a closing Flag The transmitter is not capable of sending a...

Page 198: ... a transition occurs earlier or later than expected the count will be modified during the next count cycle If the transition occurs earlier than expected it means that the bit cell boundaries are early with respect to the DPLL tracked bit cell boundaries so the count is shortened either by one or two counts If the transition occurs later than expected it means that the bit cell boundaries are late...

Page 199: ...between the sending data rate and the DPLL output clock rate is 1 16 6 With Biphase data encoding the DPLL is designed to work in multiple access conditions where there may not be Flags on an idle line The DPLL will properly generate an output clock based on the first transition in the leading zero of an opening Flag Similarly only the completion of the closing Flag is necessary for the DPLL to pr...

Page 200: ...ck and immediately enters the search mode Search mode assumes that the next transition seen is a clock transition and immedi ately synchronizes to this transition No clock output is provided to the receiver during the search operation Decoding Biphase Level data requires that the data be sampled at either the quarter or three quarter point in the bit cell The DPLL here uses the quarter point to sa...

Page 201: ... This keeps the interrupt latency down and allows the fastest transmission speed on all serial ports All the serial ports will normally generate priority level 1 interrupts In exceptional circum stances one or more serial ports can be configured to use a higher priority interrupt There is an exception to be aware of when a serial port has to operate at an extremely high speed At 115 200 bps the hi...

Page 202: ...ed full If the out pointer plus 1 equals the in pointer the buffer is empty All increments are done in a circular fashion most easily accomplished by making the buffer a power of two in length then anding a mask after the increment The actual memory address is the pointer plus a buffer base address 12 9 1 Controlling an RS 485 Driver and Receiver RS 485 uses a half duplex method of communication O...

Page 203: ...oided because it is slow erratically sup ported by different types of hardware and usually creates more problems than it solves 12 9 4 Using A Serial Port to Generate a Periodic Interrupt A serial port may be used to generate a periodic interrupt by continuously transmitting characters Since the Tx output via Parallel Port C or D can be disabled the transmitted characters are transmitted to nowher...

Page 204: ...y with 8 data bits a check is made on each character for a 9th bit low The 9th bit or parity bit is low if bit 6 of the serial port status register SxSR is set to a 1 after the character is received If the 9th bit is not a zero then the serial port treats it as an extra stop bit So if the 9th bit low flag is not set it should be assumed that the parity bit is a 1 Setting the 9th bit high or low ca...

Page 205: ...connected after the address byte Some microprocessor serial ports have a wake up mode of operation In this mode char acters without the 9th bit set to 1 are ignored and no interrupt is generated When the start of a frame is detected an interrupt takes place on that byte If the byte contains the address of the slave then the wake up mode is turned off so that the remaining charac ters in the frame ...

Page 206: ...h the transmitter and receiver operate at approximately the same baud rate there can be a difference of up to about 5 between their baud rates Thus the receiver full and transmitter empty interrupts will become out of phase with each other assuming that the remote station transmits without gaps between characters A counter is zeroed each time a character is received and the counter is incremented ...

Page 207: ...198 Rabbit 3000 Microprocessor ...

Page 208: ...ally it is an independent device that is used to communicate between the two processors A diagram of the slave port is shown in Figure 13 1 Figure 13 1 Rabbit Slave Port The slave port has three data registers for each direction of communication Three regis ters named SPD0R SPD1R and SPD2R can be written by the master and read by the slave Three different registers also named SPD0R SPD1R and SPD2R...

Page 209: ... reg ister is written to and the flag is set to a 0 when the register is read The registers appear to be internal I O registers to the slave To the master at least for a Rabbit master the registers appear to be external I O registers The figure below shows the sequence of events when the master reads writes the slave port registers Figure 13 2 Slave Port R W Sequencing SCS SD 7 0 SRD Slave Port Re...

Page 210: ...er Either side that is interrupted can clear the signal that is causing an interrupt request by writ ing to the slave port status register The data bits are ignored but the flip flop that is the source of the interrupt request is cleared Figure 13 3 shows a logical schematic of this func tionality Symbol Parameter Minimum ns Maximum ns Tsu SCS SCS Setup Time 5 Th SCS SCS Hold Time 0 Tsu SA SA Setu...

Page 211: ...he slaves Each Rabbit in Figure 13 4 has to have RAM memory The master must also have flash memory However the slaves do not need nonvolatile memory since the master can cold boot them over the slave port and download their program In order for this to happen the SMODE0 and SMODE1 pins must be properly configured as shown in Figure 13 4 to begin a cold boot process at the end of the slave reset Ma...

Page 212: ... write requests unless the chip select is low If a Rabbit is used as a master this line can be connected to one of the master s programmable chip select lines I0 I7 SRD Input If SCS is also low this line pulled low causes the contents of the register selected by the address lines to be driven on the data bus If a Rabbit is used as a master this line is normally connected to the global I O read str...

Page 213: ...d number of lifetime writes to flash memory The slaves reset in Figure 13 4 is under the program control of the master If the master is reset the slave will also be reset because the master s drive of the reset line will be lost on reset and the pull down resistor will pull the slaves resets low This may be undesirable because it forces the slave to crash if the master crashes and has a watchdog t...

Page 214: ... 1 after the reset ends This features disables the normal operation of the processor and causes commands to be accepted via the slave port register SPD0R These commands cause data to be stored in memory or I O space When the master that is managing the cold boot has finished setting up memory and I O space the SMODE1 SMODE0 pins are changed to code 0 0 which causes execution to start at address ze...

Page 215: ...13 3 1 Slave Applications Motion Controller Many types of motion control require fast action may be com pute intensive or both Traditional servo system solutions may be overly expensive or not work very well because of system nonlinearities The basic communications model for a motion controller is for the master to send short messages positioning com mands to the slave The slave acknowledges execu...

Page 216: ...pt in the master by storing a dummy character in SPD0R to cre ate a master interrupt assuming that the SLAVEATTN line is wired to interrupt the mas ter The acknowledgement message works in a similar manner except that the master writes a dummy character to interrupt the slave to say that it has the character Several problems can arise if there are dual interrupts for each character transmitted One...

Page 217: ...ave will write to SPD0R when there is a change of status on one of the serial ports The slave can interrupt the master at any time by storing to SPD0R It will do this every time an enabled transmitter is ready to accept a character or every time an enabled receiver receives a character When it stores to SPD0R it will store a code indicating the reason for the interrupt that is receive or transmit ...

Page 218: ...components to use in the oscillator circuit Figure 14 1 Rabbit 3000 Main Oscillator Circuit NOTE You may have to adjust resistors and capacitors for various frequencies and crystal load capacitances The 32 768 kHz oscillator is slow to start oscillating after power on For this reason a wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing the startup procedur...

Page 219: ...current is reduced in proportion to the operating voltage The Rabbit 3000 does not have a standby mode that some microprocessors have Instead the Rabbit has the ability to switch its clock to the 32 768 kHz oscillator This is called the sleepy mode When this is done the power consumption is decreased dramatically The current consumption is often reduced to the region of 100 µA at this clock speed ...

Page 220: ...er is measured by using a quasi peak detector in the spectrum analyzer The quasi peak detector has a charge time constant of 1 ms and a discharge time constant of 550 ms In this manner the peak radiated signal strength is measured The tests required by the FCC and the EC are practically identical The Rabbit 3000 has important features that aid in the control if EMI The power supply for the process...

Page 221: ... the energy of a given harmonic over a wider bandwidth will decrease the amount of EMI measured for a given harmonic The spectrum spreader not only reduces the EMI measured in government tests but it will also often reduce the interference cre ated for radio and television reception The spectrum spreader has three settings under software control see Table 15 1 and Table 15 2 off standard spreading...

Page 222: ...the input oscillator frequency is 4 MHz or less the spectrum spreader modulation of fre quency will enter the audio range of 20 kHz or less and may generate an audible whistle in FM stations For this reason it may be desirable to disable the spreader for low speed oscil lators where it is probably unnecessary anyway However in practical cases the whistle may not be audible due to the very low leve...

Page 223: ...The effect of a pure harmonic on TV reception is to create a herringbone pattern created by a harmonic falling within the station s band If the spreader is engaged the pattern will disappear unless the station is very weak in which case the interference will be seen as noise distrib uted over the screen ...

Page 224: ...nchronized with the internal clock The internal clock is closely synchronized with the external clock CLK that may be optionally output from pin 2 of the TQFP package The delay in signal output depends on the capacitive load on the output lines In the case of the address lines which are critically important for establishing memory access time requirements the capacitive loading is usually in the r...

Page 225: ...ve The shortening takes place by shortening the high part of the clock If the doubler is not enabled then every clock is shortened during the low part of the clock period The maxi mum shortening for a pair of clocks combined is shown in the table Table 16 2 Data and Clock Delays VDD 10 Temp 40 C 85 C maximum VDD Clock to Address Output Delay ns Data Setup Time Delay ns Spectrum Spreader Delay ns 3...

Page 226: ...s per bus cycle plus any wait states that might be specified Figure 16 2 Memory Read and Write Cycles Tadr Tadr Memory Read no wait states CLK A 19 0 Memory Write no extra wait states CLK A 19 0 valid T1 T2 T1 Tw T2 valid TOEx TOEx D 7 0 valid Thold Tsetup CSx OEx TCSx TCSx valid D 7 0 TDHZV TDVHZ CSx WEx TCSx TCSx TWEx TWEx ...

Page 227: ...y Read Time Delays Time Delay Output Capacitance 30 pF 60 pF 90 pF Max clock to address delay Tadr 6 ns 8 ns 11 ns Max clock to memory chip select delay TCSx 6 ns 8 ns 11 ns Max clock to memory read strobe delay TOEx 6 ns 8 ns 11 ns Min data setup time Tsetup 1 ns Min data hold time Thold 0 ns Table 16 4 Memory Write Time Delays Time Delay Output Capacitance 30 pF 60 pF 90 pF Max clock to address ...

Page 228: ...y Output Enable and Write Enable Timing Tadr Tadr Memory Read no wait states CLK A 19 0 Memory Write no extra wait states CLK A 19 0 valid T1 T2 T1 Tw T2 valid TOEx TOEx D 7 0 valid Thold Tsetup CSx OEx TCSx TCSx valid D 7 0 TDHZV TDVHZ CSx WEx TCSx TCSx TWEx TWEx ...

Page 229: ...ing due to the clock spectrum spreader from 2T Example clock 29 49 MHz T 34 ns operating voltage is 3 3 V bus loading is 60 pF address to output time 8 ns see Table 16 2 data setup time 1 ns the spectrum spreader is on in normal mode resulting in a loss of 3 ns The access time is given by access time 2T clock to address data setup spreader delay 68 ns 8 ns 1 ns 3 ns 56 ns data out address memory a...

Page 230: ...t to variation arising from process variation operating voltage and temperature Minimum and maximum clock low times for various doubler settings are given in the formulas and in the graph below Max delay 3 3 V 6 1 1 21 n 6 n is the nominal delay 6 20 ns Min delay 3 3 V 3 7 0 75 n 6 Max delay 2 5 V 7 6 1 67 n 6 Min delay 2 5 V 4 7 1 03 n 6 Max delay 1 8 V 12 2 2 7 n 6 Min delay 1 8 V 6 6 1 44 n 6 F...

Page 231: ...ction for the asymmetry of the original oscillator clock Example Clock 29 49 MHz T 34 ns operating voltage is 3 3 V the clock doubler has a nominal delay of 16 ns resulting in a minimum clock low time of 12 8 ns the spectrum spreader is on in normal mode resulting in a loss of 3 ns clock to output enable is 5 ns assuming 20 pF load the clock asymmetry is 52 48 resulting in a loss of 4 of the clock...

Page 232: ...ammed to be active low default or active high Tadr Tadr External I O Read no extra wait states CLK A 15 0 External I O Write no extra wait states CLK A 15 0 IORD valid T1 Tw T1 Tw T2 valid T2 BUFEN IOCSx IOWR BUFEN D 7 0 valid Tsetup Thold CSx IOCSx TCSx TIOCSx TIORD TBUFEN TCSx TIOCSx TIORD TBUFEN valid D 7 0 CSx TCSx TIOCSx TIOWR TCSx TIOCSx TIOWR TBUFEN TBUFEN TDHZV TDVHZ ...

Page 233: ...ax clock to address delay Tadr 6 ns 8 ns 11 ns Max clock to memory chip select delay TCSx 6 ns 8 ns 11 ns Max clock to I O chip select delay TIOCSx 6 ns 8 ns 11 ns Max clock to I O read strobe delay TIORD 6 ns 8 ns 11 ns Max clock to I O buffer enable delay TBUFEN 6 ns 8 ns 11 ns Min data setup time Tsetup 1 ns Min data hold time Thold 0 ns Table 16 6 I O Write Time Delays Time Delay Output Capaci...

Page 234: ...eader is enabled clock periods are shortened by a small amount depending on whether the normal or the strong spreader setting is used and depending on the operating voltage If the clock doubler is used the spectrum spreader affects every other cycle and reduces the clock high time If the doubler is not used then the spreader affects every clock cycle and the clock low time is reduced Of course the...

Page 235: ...iming Oscillator Oscillator delayed and inverted Doubled clock Delay time 48 52 P 0 48P 0 52P 0 48P 0 52P Data out Example Write Cycle write pulse early write pulse option Example Read Cycle address CS address CS output enb early output enb option Valid data out from mem ...

Page 236: ...clock output pin pin 2 The minimum period must be increased by any amount that the clock high time is greater or less than specified in the duty cycle requirement Table 16 7 Maximum Clock Speeds at 3 3 V Preliminary Conditions Commercial Ratings Industrial Ratings Duty Cycle Requirements ns Minimum Period ns Maximum Frequency MHz Minimum Period ns Maximum Frequency MHz No doubler or spreader 17 58...

Page 237: ...minimum period of 21 ns giving a mini mum period of 24 ns and a maximum frequency of 41 6 MHz commercial Since the built in high speed oscillator buffer generates a clock that is very close to having a 50 duty cycle to obtain the highest clock speeds using the clock doubler you must use an external oscillator buffer that will allow for duty cycle adjustment by changing the resistance of the power ...

Page 238: ...umed for cal culating the current consumption estimates below A crystal frequency of 3 6864 MHz is a good choice for a low power system consuming between 2 and 18 mA at 3 3 V as the clock frequency is throttled between 0 46 MHz and 7 37 MHz The required memory access time is about 250 ns however a faster memory may result in less power since a short chip select cycle can then be used A crystal fre...

Page 239: ...Rabbit 3000 System Current vs Frequency at 3 3 V enlarged view over 0 16 MHz range 0 20 40 60 80 100 120 0 10 20 30 40 50 60 Clock Frequency MHz I mA xtal 25 80 xtal 14 74 xtal 11 05 xtal 3 68 0 5 10 15 20 25 30 35 40 0 2 4 6 8 10 12 14 16 Clock Frequency MHz I mA xtal 25 80 xtal 14 74 xtal 11 05 xtal 3 68 ...

Page 240: ...sists of the processor core the external recom mended external tiny logic 32 kHz oscillator and the memory The oscillator consumes 17 µA at 3 3 V and this drops rapidly to about 2 µA at 1 8 V The processor core con sumes between 3 and 50 µA at 3 3 V as the frequency is throttled from 2 kHz to 32 kHz and about 40 as much at 1 8 V If the flash memory specified above is used for memory and a self tim...

Page 241: ...as the voltage drops and becomes negligible at 1 4 V 3 The current consumed by the built in main oscillator when turned on This current is also proportional to Vc and is equal to 1 mA at 3 3 V 4 The current drawn by the logic that is driven at the oscillator crystal frequency This is considered distinct because it varies with the crystal frequency but is not reduced when the clock frequency is div...

Page 242: ... by Itotal µA 0 32 V f 0 23 Vc f 5 Vc where f is in kHz V is the operating voltage and Vc V V 2 0 7 Leakage the standby current of the reset generator the current consumption of the oscilla tor and the real time clock and the current consumption of memories must be added to the sleepy mode current consumption Generally the self timed chip select mode is used to reduce memory current consumption ...

Page 243: ...ip select duty cycle The dynamic part is computed using 0 5 f in mA where f is the bus speed in MHz At 0 46 MHz 3 68 MHz 8 and using a short chip select the duty cycle is about 10 giving a static current of about 0 35 mA The dynamic current is 0 25 mA for a total cur rent of 0 6 mA Added to the approximately 2 5 mA operating current gives a total current of 3 1 mA at 0 46 MHz In sleepy mode with a...

Page 244: ...5 V2 0 31 V Generally the oscillator will not start unless the voltage is about 1 4 V However the oscil lator will continue to run until the voltage drops to about 0 8 V If the oscillator stops the current draw is very much lower than when it is running Below about 1 4 V most of the current draw is used to charge and discharge the capacitive load The current consumed by the battery backed portion ...

Page 245: ...ors Figure 16 13 Reduced Power External Main Oscillator Table 16 8 lists results for the reduced power external oscillator with no current limiting resistors Design Recommendations Add current limiting resistors to reduce current without inhibiting oscillator start up Increase the 1 MΩ resistor to improve gain Minimize loop area to reduce EMI Table 16 8 Current Draw Using Reduced Power External Os...

Page 246: ...from the user s application It occupies space at the bot tom of the root code segment When execution of the user s program starts at address zero on power up or reset it starts in the BIOS When Dynamic C cold boots the target and downloads the binary image of the BIOS the BIOS symbol table is retained to make its entry points and global data available to the user application Board specific drivers...

Page 247: ... it is possible to substitute a different periodic interrupt This alternative is not supported by Z World since the cost of connecting a crys tal is very small The periodic interrupt keeps the interrupts turned off that is the proces sor priority is raised to 1 from zero for about 75 clocks so it contributes little to interrupt latency The periodic interrupt is turned on by default before main is ...

Page 248: ... use virtual watchdogs for other code that must be run periodically If hits to the hardware watchdog are scattered through a program then it may be possible for the code to enter an endless loop where the watchdog is hit and therefore rendered useless for detecting the endless loop condition If no virtual watchdogs are used an undetected endless loop con dition could still occur since the periodic...

Page 249: ...240 Rabbit 3000 Microprocessor ...

Page 250: ... 32 kHz clock speeds simply because there are not enough clock cycles available to service the interrupt Hence virtual watchdogs which depend on the periodic interrupt cannot be used in the sleepy mode The user must set up an endless loop to determine when to exit sleepy mode A routine updateTimers is provided to update the system timer variables by directly reading the real time clock and to hit ...

Page 251: ... available to read and write I O registers These functions are pro vided for convenience For speed assembly code is recommended For a complete description of the functions noted in this section refer to the Dynamic C User s Manual or from the Help menu in Dynamic C access the HTML Function Reference or Function Lookup options To read internal I O registers there are two functions int RdPortI int P...

Page 252: ... I O register A NULL pointer may replace the pointer to a shadow register as an argument to WrPortI and WrPortE the shadow register associated with the port will not be updated A pointer to the shadow register is mandatory for BitWrPortI and BitWrPortE 18 3 2 Interrupt While Updating Registers When manipulating I O registers and shadow registers the programmer must keep in mind that an interrupt c...

Page 253: ...the data bits written are ignored For example a write to the status register in the Rabbit serial ports is used to clear the transmitter interrupt request but the data bits are ignored and the status register is actually a read only register except for the special functionality attached to the act of writing the register An illustration of a write only register for which a shadow is unnecessary is...

Page 254: ...same oscillator as the real time clock there is no relative gain or loss of time between the two A millisecond timer variable MS_TIMER is also maintained by the Virtual Driver Two utility routines are provided that can be used to convert times between the traditional format 10 Jan 2000 17 34 12 and the seconds since 1 Jan 1980 format converts time structure to seconds unsigned long mktime struct t...

Page 255: ...246 Rabbit 3000 Microprocessor ...

Page 256: ...ation Instructions on page 252 16 bit Arithmetic and Logical Ops on page 252 8 bit Arithmetic and Logical Ops on page 253 8 bit Bit Set Reset and Test on page 254 8 bit Increment and Decrement on page 254 8 bit Fast A Register Operations on page 255 8 bit Shifts and Rotates on page 255 Instruction Prefixes on page 256 Block Move Instructions on page 256 Control Instructions Jumps and Calls on page...

Page 257: ... IOI and IOE affect source S Z L V The L V logical overflow flag serves a dual purpose L V is set to 1 for logical operations if any of the four most significant bits of the result are 1 and L V is reset to 0 if all four of the most significant bits of the result are 0 C Description Sign flag affected Sign flag not affected Zero flag affected Zero flag not affected L LV flag contains logical check...

Page 258: ...carry 100 LZ logical zero 101 LO logical one 110 P sign plus 111 M sign minus Logical zero if all four of the most significant bits of the result are 0 Logical one if any of the four most significant bits of the result are 1 m m MSB of a 16 bit constant mn mn 16 bit constant n n 8 bit constant or LSB of a 16 bit constant r g g g Byte register select 000 B 001 C 010 D 011 E 100 H 101 L 111 A ss ww ...

Page 259: ... I S Z V C Operation LD A BC 6 r s A BC LD A DE 6 r s A DE LD BC A 7 d BC A LD DE A 7 d DE A LD HL n 7 d HL n LD HL r 6 d HL r B C D E H L A LD r HL 5 r s r HL LD IX d n 11 d IX d n LD IX d r 10 d IX d r LD r IX d 9 r s r IX d LD IY d n 11 d IY d n LD IY d r 10 d Iy d r LD r IY d 9 r s r IY d 19 4 16 bit Indexed Loads and Stores Instruction clk A I S Z V C Operation LD HL d HL 13 d HL d L HL d 1 H...

Page 260: ... a 64K page boundary Since the LDP instruc tion operates on two byte values the second byte will wrap around and be written at the start of the page if you try to read or write across a page boundary Thus if you fetch or store at address 0xn 0xFFFF you will get the bytes located at 0xn 0xFFFF and 0xn 0x0000 instead of 0xn 0xFFFFand 0x n 1 0x0000 as you might expect Therefore do not use LDP at any ...

Page 261: ...on ADD SP d 4 f SP SP d d 0 to 255 POP IP 7 IP SP SP SP 1 POP IX 9 IXL SP IXH SP 1 SP SP 2 POP IY 9 IYL SP IYH SP 1 SP SP 2 POP zz 7 r zzl SP zzh SP 1 SP SP 2 zz BC DE HL AF PUSH IP 9 SP 1 IP SP SP 1 PUSH IX 12 SP 1 IXH SP 2 IXL SP SP 2 PUSH IY 12 SP 1 IYH SP 2 IYL SP SP 2 PUSH zz 10 SP 1 zzh SP 2 zzl SP SP 2 zz BC DE HL AF 19 9 16 bit Arithmetic and Logical Ops Instruction clk A I S Z V C Operati...

Page 262: ... DE 4 f L 0 IY IY DE RL DE 2 fr L CY DE DE CY left shift with CF RR DE 2 fr L DE CY CY DE RR HL 2 fr L HL CY CY HL RR IX 4 f L IX CY CY IX RR IY 4 f L IY CY CY IY SBC HL ss 4 fr V HL HL ss CY cout if ss CY hl 19 10 8 bit Arithmetic and Logical Ops Instruction clk A I S Z V C Operation ADC A HL 5 fr s V A A HL CF ADC A IX d 9 fr s V A A IX d CF ADC A IY d 9 fr s V A A IY d CF ADC A n 4 fr V A A n C...

Page 263: ... instruction output inverted carry C is set if A B if the oper ation or virtual operation is A B Carry is cleared if A B SUB outputs carry in opposite sense from SBC and CP 19 11 8 bit Bit Set Reset and Test Instruction clk A I S Z V C Operation BIT b HL 7 f s HL bit BIT b IX d 10 f s IX d bit BIT b IY d 10 f s IY d bit BIT b r 4 f r bit RES b HL 10 d HL HL bit RES b IX d 13 d IX d IX d bit RES b ...

Page 264: ...HL HL 6 0 HL 7 CY HL 7 RLC IX d 13 f b L IX d IX d 6 0 IX d 7 CY IX d 7 RLC IY d 13 f b L IY d IY d 6 0 IY d 7 CY IY d 7 RLC r 4 fr L r r 6 0 r 7 CY r 7 RR HL 10 f b L HL CY CY HL RR IX d 13 f b L IX d CY CY IX d RR IY d 13 f b L IY d CY CY IY d RR r 4 fr L r CY CY r RRC HL 10 f b L HL HL 0 HL 7 1 CY HL 0 RRC IX d 13 f b L IX d IX d 0 IX d 7 1 CY IX d 0 RRC IY d 13 f b L IY d IY d 0 IY d 7 1 CY IY...

Page 265: ...tes enabled The V flag is set when BC transitions from 1 to 0 If the V flag is not set another step is performed for the repeating versions of the instructions Interrupts can occur between dif ferent repeats but not within an iteration equivalent to LDD or LDI Return from the inter rupt is to the first byte of the instruction which is the I O prefix byte if there is one A new LDIR LDDR bug was dis...

Page 266: ...C mn LRET 13 PCL SP PCH SP 1 XPC SP 2 SP SP 3 RET 8 PCL SP PCH SP 1 SP SP 2 RET f 8 2 if f PCL SP PCH SP 1 SP SP 2 RETI 12 IP SP PCL SP 1 PCH SP 2 SP SP 3 RST v 10 SP 1 PCH SP 2 PCL SP SP 2 PC R v v 10 18 20 28 38 only 19 18 Miscellaneous Instructions Instruction clk A I S Z V C Operation CCF 2 f CF CF IPSET 0 4 IP IP 5 0 00 IPSET 1 4 IP IP 5 0 01 IPSET 2 4 IP IP 5 0 10 IPSET 3 4 IP IP 5 0 11 IPRE...

Page 267: ...ver growing stack RETI pops IP from stack and then pops return address The instruction reti can be used to set both the return address and the IP in a single instruction If preceded by a LD XPC a complete jump or call to a computed address can be done with no possible interrupt LD A XPC get and set the XPC LD XPC A The instruction LD XPC A is privileged so that it can be followed by other code set...

Page 268: ...a practical op code The codes that are concerned with decimal arithmetic DAA RRD and RLD could be simulated but the simulation is very inefficient The bit in the status register used for half carry is available and can be set and cleared using the PUSH AF and POP AF instructions to gain access Usually code that uses these instructions should be rewritten The instructions CPI CPIR CPD and CPDR are ...

Page 269: ... LD A IIR was I register The following Z80 Z180 instructions have been dropped and are not supported Alterna tive Rabbit instructions are provided Z80 Z180 Instructions Dropped Rabbit Instructions to Use CALL CC ADR JR JP ncc xxx reverse condition CALL ADR xxx TST R HL n PUSH DE PUSH AF AND r HL n POP DE get a in h LD A d POP DE ...

Page 270: ...n s IOI and IOE affect source Flag Register Key S Z L V The L V logical overflow flag serves a dual purpose L V is set to 1 for logical operations if any of the four most signif icant bits of the result are 1 and L V is reset to 0 if all four of the most significant bits of the result are 0 C Description Sign flag affected Sign flag not affected Zero flag affected Zero flag not affected L L V flag...

Page 271: ...011 C carry 100 LZ logical zero 101 LO logical one 110 P sign plus 111 M sign minus Logical zero if all four of the most significant bits of the result are 0 Logical one if any of the four most significant bits of the result are 1 m m MSB of a 16 bit constant mn mn 16 bit constant n n 8 bit constant or LSB of a 16 bit constant r g g g Byte register select 000 B 001 C 010 D 011 E 100 H 101 L 111 A ...

Page 272: ...E 11011101 11011100 4 f L 0 AND IY DE 11111101 11011100 4 f L 0 AND n 11100110 n 4 fr L 0 AND r 10100 r 2 fr L 0 BIT b HL 11001011 01 b 110 7 f s BIT b IX d 11011101 11001011 d 01 b 110 10 f s BIT b IY d 11111101 11001011 d 01 b 110 10 f s BIT b r 11001011 01 b r 4 f BOOL HL 11001100 2 fr 0 0 BOOL IX 11011101 11001100 4 f 0 0 BOOL IY 11111101 11001100 4 f 0 0 CALL mn 11001101 n m 12 CCF 00111111 2...

Page 273: ...m 7 JP mn 11000011 n m 7 JR cc e 001cc000 e 2 5 JR e 00011000 e 2 5 Note If byte following op code is zero next sequential instruction is executed If byte is 2 11111110 jr is to itself LCALL xpc mn 11001111 n m xpc 19 LD BC A 00000010 7 d LD DE A 00010010 7 d LD HL n 00110110 n 7 d LD HL r 01110 r 6 d LD HL d HL 11011101 11110100 d 13 d LD IX d HL 11110100 d 11 d LD IX d n 11011101 00110110 d n 11...

Page 274: ...mn 11011101 00101010 n m 13 s LD IX SP n 11011101 11000100 n 11 LD IX HL 11011101 01111101 4 LD IX mn 11011101 00100001 n m 8 LD IY mn 11111101 00101010 n m 13 s LD IY SP n 11111101 11000100 n 11 LD IY HL 11111101 01111101 4 LD IY mn 11111101 00100001 n m 8 LD r HL 01 r 110 5 r s LD r IX d 11011101 01 r 110 d 9 r s LD r IY d 11111101 01 r 110 d 9 r s LD r g 01 r g 2 r LD r n 00 r 110 n 4 r LD SP H...

Page 275: ...1011101 11100101 12 PUSH IY 11111101 11100101 12 PUSH zz 11zz0101 10 RES b HL 11001011 10 b 110 10 d RES b IX d 11011101 11001011 d 10 b 110 13 d RES b IY d 11111101 11001011 d 10 b 110 13 d RES b r 11001011 10 b r 4 r RET 11001001 8 RET f 11 f 000 8 2 RETI 11101101 01001101 12 RL HL 11001011 00010110 10 f b L RL IX d 11011101 11001011 d 00010110 13 f b L RL IY d 11111101 11001011 d 00010110 13 f ...

Page 276: ...001011 00100110 10 f b L SLA IX d 11011101 11001011 d 00100110 13 f b L SLA IY d 11111101 11001011 d 00100110 13 f b L SLA r 11001011 00100 r 4 fr L SRA HL 11001011 00101110 10 f b L SRA IX d 11011101 11001011 d 00101110 13 f b L SRA IY d 11111101 11001011 d 00101110 13 f b L SRA r 11001011 00101 r 4 fr L SRL HL 11001011 00111110 10 f b L SRL IX d 11011101 11001011 d 00111110 13 f b L SRL IY d 111...

Page 277: ...268 Rabbit 3000 Microprocessor ...

Page 278: ...arget reset line which should be drivable by an external CMOS driver The STATUS pin is used to by the Rabbit based target to request attention when a breakpoint is encountered in the target under test The SMODE pins are pulled up by a 5 V 3 V level from the interface They should be pulled down on the board when the interface is not in use by approximately 5 kΩ resistors to ground The target under ...

Page 279: ...on needs to begin or to enable the port and wait for interrupts The SMODE pins can be used for signaling and can be detected by a poll However recall that the SMODE pins have a special function after reset and will inhibit normal reset behavior if not held low The pull up resistors on RXA and CLKA prevent spurious data reception that might take place if the pins floated If the clocked serial mode ...

Page 280: ...vent overrunning the receiver the target can wait for a handshake signal on one of the SMODE lines or there can be suitable pre arranged delays If the PC wants attention from the target it can set a line to request attention SMODE The target will detect this line in the periodic interrupt routine and handle the complete message in the periodic interrupt routine This may slow down target execution ...

Page 281: ...d 1 8432 3 6864 271 522 4 3 6864 7 3728 136 257 8 7 3728 14 7456 68 124 16 9 216 18 432 54 97 20 11 0592 22 1184 45 79 24 12 9024 25 8048 39 67 28 14 7456 29 4912 34 57 32 18 432 36 864 27 44 40 22 1184 44 2368 23 35 48 25 8048 51 6096 19 29 56 Non Stock Crystals 20 2752 40 5504 25 39 44 21 1968 42 3936 24 37 46 23 04 46 08 22 33 50 23 9616 47 9232 21 32 52 24 8832 49 7664 20 30 54 26 7264 53 4528...

Page 282: ...number of wait states for both the read and the write However all subse quent iterations use the number of waits programmed for the memory located at the write address for both the read and the write cycles This becomes a problem when moving a block of data from a slow memory device requiring wait states to a fast memory device requiring no wait states c Interrupt after I O with Short CSx enabled ...

Page 283: ...the periodic interrupt f Two new opcodes were added to support multiply and add and multiply and subtract operations on large unsigned integers These operations can be used to speed up public key calculations g Six new opcodes were added to support block copy operations from I O addresses to memory addresses and vice versa h The I O address space has been expanded to 16 bits to make room for new p...

Page 284: ...nd Serial Ports E and F transmit and receive clocks on other pins n The Schmitt trigger IC normally required for the low power 32 768 kHz oscil lator circuit is now integrated inside the Rabbit 3000A NOTE Based on this modification a new low power oscillator circuit is recommended for use with Rabbit 3000A based systems Please refer to TN235 External 32 768 kHz Oscillator Circuits for more informa...

Page 285: ... protection scheme X Stack protection X RAM segment relocation X Secondary watchdog timer X Multiply add and multiply subtract X Variants of block move opcodes X 16 bit internal I O address space X External I O interface enhancements X Expanded low power capability X PWM improvements X Quadrature decoder improvements X Integrated Schmitt trigger for 32 kHz oscillator input X Alternate output port ...

Page 286: ...ister WPSALR 0x0481 W 00000000 Write Protect Segment A High Register WPSAHR 0x0482 W 00000000 Write Protect Segment B Register WPSBR 0x0484 W 00000000 Write Protect Segment B Low Register WPSBLR 0x0485 W 00000000 Write Protect Segment B High Register WPSBHR 0x0486 W 00000000 Real Time Clock User Enable Register RTUER 0x0300 W 00000000 Slave Port User Enable Register SPUER 0x0320 W 00000000 Paralle...

Page 287: ...000 Serial Port C User Enable Register SCUER 0x03E0 W 00000000 Serial Port D User Enable Register SDUER 0x03F0 W 00000000 Serial Port E User Enable Register SEUER 0x03C8 W 00000000 Serial Port F User Enable Register SFUER 0x03D8 W 00000000 Enable Dual Mode Register EDMR 0x0420 W 00000000 Quad Decode Count1 High Register QDC1HR 0x0095 R xxxxxxxx Quad Decode Count 2 High Register QDC2HR 0x0097 R xxx...

Page 288: ...W 000000xx 00000000 I O Bank 1 Control Register IB1CR 0x0081 W 000000xx 00000000 I O Bank 2 Control Register IB2CR 0x0082 W 000000xx 00000000 I O Bank 3 Control Register IB3CR 0x0083 W 000000xx 00000000 I O Bank 4 Control Register IB4CR 0x0084 W 000000xx 00000000 I O Bank 5 Control Register IB5CR 0x0085 W 000000xx 00000000 I O Bank 6 Control Register IB6CR 0x0086 W 000000xx 00000000 I O Bank 7 Con...

Page 289: ...0060 0x006F No interrupts Parallel Port E 0x0070 0x007F No interrupts External I O Control 0x0080 0x0087 No interrupts Pulse Width Modulator 0x0088 0x008F No interrupts Quadrature Decoder 0x0090 0x0097 IIR 7 1 1 0x90 External Interrupts 0x0098 0x009F INT0 EIR 0x00 INT1 EIR 0x10 Timer A 0x00A0 0x00AF IIR 7 1 0 0xA0 Timer B 0x00B0 0x00BF IIR 7 1 0 0xB0 Serial Port A async cks 0x00C0 0x00C7 IIR 7 1 0...

Page 290: ...Watchdog 0x000C IIR 7 1 0 0x10 Stack Limit Violation n a IIR 7 1 1 0xB0 Write Protection Violation n a IIR 7 1 0 0x90 System Mode Violation n a IIR 7 1 1 0x80 Table B 4 Rabbit 3000 I O Address Ranges and Interrupt Service Vectors continued continued On Chip Peripheral I O Address Range ISR Starting Address ...

Page 291: ... GCPU and the other register is reserved for revision identification GREV The CPU identification GCPU of all revisions of the Rabbit 3000 microprocessor is the same Rabbit 3000 revi sions are differentiated by the value in the GREV register Table B 5 summarizes the processor identification information for the different Rabbit 3000 versions Table B 5 Rabbit 3000 Revision Identification Information ...

Page 292: ...be enabled for User mode access in the User Enable registers listed below When enabled for User mode access a peripheral interrupt if it is capable of gen erating an interrupt can only be requested at interrupt priority level 2 or 1 and it is assumed that the interrupt service routine will be executed by User mode code Note that the processor automatically enters the System mode when entering the ...

Page 293: ...e protection can be enabled for the User mode only or for all modes see Appendix C for more information Figure B 1 Sample Memory Protection Layout The new memory protection registers are listed in Table B 6 through Table B 11 Table B 6 Write Protect Control Register Write Protect Control Register WPCR Address 0x0440 Bit s Value Description 7 1 These bits are reserved and should be written with zer...

Page 294: ... physical address 0x50000 0x5FFFF 4 0 Disable 64Kwrite protect for physical address 0x40000 0x4FFFF 1 Enable 64K write protect for physical address 0x40000 0x4FFFF 3 0 Disable 64K write protect for physical address 0x30000 0x3FFFF 1 Enable 64Kwrite protect for physical address 0x30000 0x3FFFF 2 0 Disable 64K write protect for physical address 0x20000 0x2FFFF 1 Enable 64K write protect for physical...

Page 295: ...3 0 Disable 64K write protect for physical address 0xB0000 0xBFFFF 1 Enable 64K write protect for physical address 0xB0000 0xBFFFF 2 0 Disable 64K write protect for physical address 0xA0000 0xAFFFF 1 Enable 64K write protect for physical address 0xA0000 0xAFFFF 1 0 Disable 64K write protect for physical address 0x90000 0x9FFFF 1 Enable 64K write protect for physical address 0x90000 0x9FFFF 0 0 Dis...

Page 296: ...set 0x5000 0x5FFF in WP Segment x 4 0 Disable 4K write protect for address offset 0x4000 0x4FFF in WP Segment x 1 Enable 4K write protect for address offset 0x4000 0x4FFF in WP Segment x 3 0 Disable 4K write protect for address offset 0x3000 0x3FFF in WP Segment x 1 Enable 4K write protect for address offset 0x3000 0x3FFF in WP Segment x 2 0 Disable 4K write protect for address offset 0x2000 0x2FF...

Page 297: ...ress offset 0xD000 0xDFFF in WP Segment x 4 0 Disable 4K write protect for address offset 0xC000 0xCFFF in WP Segment x 1 Enable 4K write protect for address offset 0xC000 0xCFFF in WP Segment x 3 0 Disable 4K write protect for address offset 0xB000 0xBFFF in WP Segment x 1 Enable 4K write protect for address offset 0xB000 0xBFFF in WP Segment x 2 0 Disable 4K write protect for address offset 0xA0...

Page 298: ...ack is placed against a memory segment boundary Figure B 2 shows one possible stack layout A 2048 byte stack is set up by setting STKHLR to 0xE0 STKLLR to 0xD8 and SP to 0xDFF0 Any stack relative memory accesses above 0xDFEF i e stack underflow or below 0xD810 i e overflow would trigger the stack violation interrupt Figure B 2 Simple Stack Protection Layout Stack access in this region triggers an ...

Page 299: ...mit Register Stack Low Limit Register STKLLR Address 0x0445 Bit s Value Description 7 0 Lower limit for stack limit checking If a stack operation or stack relative memory access is attempted at an address less than STKLLR 0x10 a stack limit violation interrupt is generated Table B 14 Stack High Limit Register Stack High Limit Register STKHLR Address 0x0446 Bit s Value Description 7 0 Upper limit f...

Page 300: ...lows a 1 2 or 4 KB segment of the logical memory space to be mapped as data would be mapped even for program execution Table B 15 RAM Segment Register RAM Segment Register RAMSR Address 0x0448 Bit s Value Description 7 2 Compare value for RAM segment limit checking 1 0 00 Disable RAM segment limit checking 01 Select data type MMU translation if PC 15 10 is equal to RAMSR 7 2 10 Select data type MM...

Page 301: ...he System User mode is enabled it can be used as a configurable periodic interrupt as well Table B 16 Watchdog Timer Control Register Updated Watchdog Timer Control Register WDTCR Address 0x0008 Bit s Value Description 7 0 0x5A Restart the watchdog timer with a 2 second time out period 0x57 Restart the watchdog timer with a 1 second time out period 0x59 Restart the watchdog timer with a 500 ms tim...

Page 302: ...his fundamental operation allows the addition or subtraction of two arbitrarily long unsigned integers after one is scaled by a single byte value This operation is common in many cryptographic operations Table B 18 New Rabbit 3000 Opcodes Instruction Bytes Clks A I S Z V C Operation UMA 2 8 8i CY DE HL IX IY DE DE CY BC BC 1 IX IX 1 IY IY 1 HL HL 1 repeat while BC 0 UMS 2 8 8i CY DE HL IX IY DE DE...

Page 303: ...ads or writes to a peripheral for example a device on the external I P bus Six new block copy opcodes were added to the Rabbit 3000 revision These opcodes can copy from an I O address as well as to one and either the source or destination address can remain fixed instead of changing after each byte The new opcodes are described in Table B 19 Table B 19 Rabbit 3000 Revision Block Copy Opcode Effect...

Page 304: ...0x00FF 1 15 bit internal I O addresses address range 0x0000 0x7FFF required to access internal I O addresses of 0x0100 and higher 6 0 This bit is ignored and will always return zero when read 5 0 Enable A16 and A19 inversion independent of instruction data 1 Enable A16 and A19 inversion controlled by bits 0 3 for data accesses only This enables the instruction data split for the separate I and D s...

Page 305: ... 0x0084 IB5CR Address 0x0085 IB6CR Address 0x0086 IB7CR Address 0x0087 Bit s Value Description 7 6 00 Fifteen wait states for accesses in this bank 01 Seven wait states for accesses in this bank 10 Three wait states for accesses in this bank 11 One wait state for accesses in this bank 5 4 00 The Ix signal is an I O chip select 01 The Ix signal is an I O read strobe 10 The Ix signal is an I O write...

Page 306: ...s reserved and should not be used 100 296 ns self timed chip selects 192 ns best case 457 ns worst case 101 234 ns self timed chip selects 151 ns best case 360 ns worst case 110 171 ns self timed chip selects 111 ns best case 264 ns worst case 111 109 ns self timed chip selects 71 ns best case 168 ns worst case 4 0 Normal Chip Select timing for read cycles 1 Short Chip Select timing for read cycle...

Page 307: ...t This bit will always be read as zero 1 Force a periodic interrupt to be pending 4 2 xxx See table below for decode of this field 1 0 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Priority 3 Table B 24 Clock Select Field of GCSR Clock Select Bits 4 2 GCSR CPU Clock Peripheral...

Page 308: ...nserted between T1 and T2 so this will have no effect on the duration of the chip select signals in this mode The timing diagrams below illustrate the actual timing for the different divided cases In these cases the chip selects are two clock cycles of the fast oscillator long Figure B 3 Short Chip Select Timing CLK 8 Read Operation oscillator ADDR DATA T1 T2 Valid OEx CSx clock divide by 8 mode ...

Page 309: ...Short Chip Select Timing CLK 6 Read Operation Figure B 5 Short Chip Select Timing CLK 4 Read Operation oscillato r A D D R D A T A T 1 T 2 Valid O E x C Sx clock divide by 6 mo de oscillator ADDR DATA T1 T2 Valid OEx CSx clock divide by 4 mode ...

Page 310: ...User s Manual 301 Figure B 6 Short Chip Select Timing CLK 2 Read Operation oscillator ADDR DATA T1 T2 Valid OEx CSx clock divide by 2 mode ...

Page 311: ...below for the four different cases In these case the chip selects are one clock cycle of the 32 kHz clock long Figure B 7 Short Chip Select Timing 2 kHz Read Operation Figure B 8 Short Chip Select Timing 4 kHz Read Operation 32KHz ADDR DATA T1 T2 Valid MEMOExB MEMCSxB clock 2KHz operation OEx CSx 2 kHz operation 32 kHz 32 kHz ADDR DATA T1 T2 Valid OEx CSx clock 4 kHz operation ...

Page 312: ...B 9 Short Chip Select Timing 8 kHz Read Operation Figure B 10 Short Chip Select Timing 16 kHz Read Operation 32 kHz ADDR DATA T1 T2 Valid OEx CSx clock 8 kHz operation 32 kHz ADDR DATA T1 T2 Valid OEx CSx clock 16 kHz operation ...

Page 313: ...304 Rabbit 3000 Microprocessor Figure B 11 Short Chip Select Timing 32 kHz Read Operation 32 kHz ADDR DATA T1 T2 Valid OEx CSx clock 32 kHz operation ...

Page 314: ... the duration of the chip select signals in this mode The timing diagrams below illus trate the actual timing for the different divided cases In these cases the chip selects are active for two clock cycles before and two clock cycles after the trailing edge of the write signal Figure B 12 Short Chip Select Timing CLK 8 Write Operation oscillator ADDR DATA T1 TW A V alid W Ex CSx clock divide by 8m...

Page 315: ...Chip Select Timing CLK 6 Write Operation Figure B 14 Short Chip Select Timing CLK 4 Write Operation oscillator ADDR DATA T1 TWA Valid WEx CSx clock divide by 6 mode T2 oscillato r A D D R D A T A T 1 T W A Valid W E x C Sx clock divide by 4 mo de T 2 ...

Page 316: ...User s Manual 307 Figure B 15 Short Chip Select Timing CLK 2 Write Operation oscillator ADDR DATA T1 TWA Valid WEx CSx clock divide by 2 mode T2 ...

Page 317: ...or one clock cycle before and one clock cycle after the trailing edge of the write signal Figure B 16 Short Chip Select Timing 2 kHz Write Operation Figure B 17 Short Chip Select Timing 4 kHz Write Operation 32KHz ADDR DATA T1 TWA Valid MEMWExB MEMCSxB clock 2KHz operation T2 WEx CSx 2kHz operation 32kHz 32kHz ADDR DATA T1 TW A V alid W Ex CSx clock 4kHzoperation T2 ...

Page 318: ...hort Chip Select Timing 8 kHz Write Operation Figure B 19 Short Chip Select Timing 16 kHz Write Operation 32 kHz ADDR DATA T1 TWA Valid WEx CSx clock 8 kHz operation T2 32 kHz ADDR DATA T1 TWA Valid WEx CSx clock 16 kHz operation T2 ...

Page 319: ...310 Rabbit 3000 Microprocessor Figure B 20 Short Chip Select Timing 32 kHz Write Operation 32 kHz ADDR DATA T1 TWA Valid WEx CSx clock 32 kHz operation T2 ...

Page 320: ...of two iterations of the PWM counter The one of eight option works nicely with R C servos which require a 1 ms to 2 ms pulse width and a 20 ms period This option gives the full resolution for the pulse width while still meeting the period requirements The one of four and one of two options can be used to create more virtual PWM channels using soft ware to multiplex the PWM outputs There is a separ...

Page 321: ...rrupts use Interrupt Priority 3 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle Table B 26 PWM LSB 1 Register PWM LSB 1 Register PWL1R Address 0x008A Bit s Value Description 7 6 write The least significant two bits for the Pulse Width Modulator count are stored 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress ...

Page 322: ...Width Modulator count are stored 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 1 These bits are ignored and should be written with zero 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle ...

Page 323: ... Port F bits 7 and 6 5 0 Eight bit quadrature decoder counters 1 Ten bit quadrature decoder counters 4 This bit is reserved and should be written as zero 3 2 00 Disable Quadrature Decoder 1 inputs Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement 01 This bit combination is reserved and should not be used 10 Quadrature Decoder 1 inputs from Port F bits ...

Page 324: ... Quadrature Decode 8 bit and 10 bit Counter Timing Cnt 8 bit Interrupt I input Q input 00 01 02 03 04 05 06 07 08 07 06 05 04 03 02 01 00 FF FF Cnt 10 bit 000 001 002 003 004 005 006 007 008 007 006 005 004 003 002 001 000 3FF 3FF ...

Page 325: ...herals and are indicated by an asterisk in Table 5 2 Slave port CS ASCS Alternate slave port chip select input Serial Ports E F ARXE Alternate Serial Port E receive ARCLKE Alternate Serial Port E receive clock HDLC ARXF Alternate Serial Port F receive ARCLKF Alternate Serial Port F receive clock HDLC PWM outputs APWM3 Alternate PWM output bit 3 APWM2 Alternate PWM output bit 2 APWM1 Alternate PWM ...

Page 326: ... the user s standard code By remov ing access to the processor s I O registers and preventing memory writes to critical regions the user s code can run without the danger of locking up the processor to the point where it cannot be restarted remotely and or new code uploaded Table C 1 Differences Between System and User Modes System Mode User Mode All peripherals accessible No peripherals accessibl...

Page 327: ...ode puts the processor into the User mode by pushing the correct value into the SU register PUSH SU and POP SU push and pop the single byte SU register on off the SP stack SURES pops the current processor mode off the SU register returning it to the previous mode IDET causes an interrupt if executed in the User mode and does nothing in the System mode RDMODE returns the current mode in the carry f...

Page 328: ...t B User Enable Register PBUER 0x0340 W 00000000 Parallel Port C User Enable Register PCUER 0x0350 W 00000000 Parallel Port D User Enable Register PDUER 0x0360 W 00000000 Parallel Port E User Enable Register PEUER 0x0370 W 00000000 Parallel Port F User Enable Register PFUER 0x0338 W 00000000 Parallel Port G User Enable Register PGUER 0x0348 W 00000000 Input Capture User Enable Register ICUER 0x035...

Page 329: ...al Clock Modulator 0 Register GCM0R 0x000A Global Clock Modulator 1 Register GCM1R 0x000B Secondary Watchdog Timer Register These registers are only available on the Rabbit 3000A SWDTR 0x000C Global Power Save Control Register GPSCR 0x000D Global Output Control Register GOCR 0x000E Global Clock Double Register GCDR 0x000F MMU Instruction Data Register MMIDR 0x0010 Stack Segment Register STACKSEG 0...

Page 330: ...ple of both system and user interrupt handling is shown in Figure C 1 Figure C 1 Interrupt Handing in System User Mode Some sample code for both System mode interrupts and User mode interrupts is shown below system_isr jumped to from interrupt vector table handle interrupt sures reenter previous mode ret user_isr jumped to from interrupt vector table push su preserve current SU stack setusr enter ...

Page 331: ...vel 3 are sys tem mode violation stack limit violation write protection violation and the secondary watchdog In addition any interrupt assigned to User mode is prevented by hardware from requesting a Level 3 interrupt If a user assigned interrupt is programmed to occur at Level 3 the hardware will automatically modify the request to occur at Level 2 Within a given interrupt priority level the inte...

Page 332: ...t Capture Read the status from the ICCSR PWM Write any PWM register Slave Port Rd Read the data from the SPD0R SPD1R or SPD2R Wr Write data to the SPD0R SPD1R SPD2R or write a dummy byte to the SPSR Serial Port E Rx Read the data from the SEDR or SEAR Tx Write data to the SEDR SEAR SELR or write a dummy byte to the SESR Serial Port F Rx Read the data from the SFDR or SFAR Tx Write data to the SFDR...

Page 333: ...interrupts to be used are set up for the User mode critical memory regions are protected stack limits are set and the various system memory stack violation interrupts are enabled The processor then enters the User mode and remains in the User mode for all operations interrupts can be handled however the user desires Obviously the critical interrupts can be handled in the System mode but at that po...

Page 334: ...errupts where latency is critical By keeping the System mode code sections small potential system crashes are still mini mized An overview of this level of operation is shown in Figure C 3 Figure C 3 System User Mode Setup for Mixed Operation Return from interrupts Critical Interrupts System Mode User Mode Application code User defined interrupts Critical interrupts Time critical interrupts ...

Page 335: ...an request the particular action by loading the appropriate value into HL and executing SYSCALL This requires generating a list of all the actions that the application code would want to do assigning values to each action and implementing a SYSCALL handler in the System mode that parses the value passed to it and calls the appropriate function Write protection should be enabled User mode only for ...

Page 336: ...RTC4R 0x0006 R xxxxxxxx Real Time Clock Byte 5 Register RTC5R 0x0007 R xxxxxxxx Watchdog Timer Control Register WDTCR 0x0008 W 00000000 Watchdog Timer Test Register WDTTR 0x0009 W 00000000 Global Clock Modulator 0 Register GCM0R 0x000A W 00000000 Global Clock Modulator 1 Register GCM1R 0x000B W 00000000 Secondary Watchdog Timer Register SWDTR 0x000C W 11111111 Global Power Save Control Register GP...

Page 337: ...0000000 Write Protect Segment A Low Register WPSALR 0x0481 W 00000000 Write Protect Segment A High Register WPSAHR 0x0482 W 00000000 Write Protect Segment B Register WPSBR 0x0484 W 00000000 Write Protect Segment B Low Register WPSBLR 0x0485 W 00000000 Write Protect Segment B High Register WPSBHR 0x0486 W 00000000 Real Time Clock User Enable Register RTUER 0x0300 W 00000000 Slave Port User Enable R...

Page 338: ...00 Slave Port Data 0 Register SPD0R 0x0020 R W xxxxxxxx Slave Port Data 1 Register SPD1R 0x0021 R W xxxxxxxx Slave Port Data 2 Register SPD2R 0x0022 R W xxxxxxxx Slave Port Status Register SPSR 0x0023 R 00000000 Slave Port Control Register SPCR 0x0024 R W 0xx00000 Port A Data Register PADR 0x0030 R W xxxxxxxx Port B Data Register PBDR 0x0040 R W 00xxxxxx Port B Data Direction Register PBDDR 0x0047...

Page 339: ...Port E Bit 4 Register PEB4R 0x007C W xxxxxxxx Port E Bit 5 Register PEB5R 0x007D W xxxxxxxx Port E Bit 6 Register PEB6R 0x007E W xxxxxxxx Port E Bit 7 Register PEB7R 0x007F W xxxxxxxx Port F Data Register PFDR 0x0038 R W xxxxxxxx Port F Control Register PFCR 0x003C W xx00xx00 Port F Function Register PFFR 0x003D W xxxxxxxx Port F Drive Control Register PFDCR 0x003E W xxxxxxxx Port F Data Direction...

Page 340: ...0000 Input Capture Control Register ICCR 0x0057 W xxxxxx00 Input Capture Trigger 1 Register ICT1R 0x0058 W 00000000 Input Capture Source 1 Register ICS1R 0x0059 W xxxxxxxx Input Capture LSB 1 Register ICL1R 0x005A R xxxxxxxx Input Capture MSB 1 Register ICM1R 0x005B R xxxxxxxx Input Capture Trigger 2 Register ICT2R 0x005C W 00000000 Input Capture Source 2 Register ICS2R 0x005D W xxxxxxxx Input Cap...

Page 341: ...nt 6 Register TAT6R 0x00AD W xxxxxxxx Timer A Time Constant 7 Register TAT7R 0x00AF W xxxxxxxx Timer B Control Status Register TBCSR 0x00B0 R W xxxxx000 Timer B Control Register TBCR 0x00B1 W xxxx0000 Timer B MSB 1 Register TBM1R 0x00B2 W xxxxxxxx Timer B LSB 1 Register TBL1R 0x00B3 W xxxxxxxx Timer B MSB 2 Register TBM2R 0x00B4 W xxxxxxxx Timer B LSB 2 Register TBL2R 0x00B5 W xxxxxxxx Timer B Cou...

Page 342: ...p Register SDLR 0x00F2 W xxxxxxxx Serial Port D Status Register SDSR 0x00F3 R 0xx00000 Serial Port D Control Register SDCR 0x00F4 W xx000000 Serial Port D Extended Register SDER 0x00F5 W 00000000 Serial Port E Data Register SEDR 0x00C8 R W xxxxxxxx Serial Port E Address Register SEAR 0x00C9 W xxxxxxxx Serial Port E Long Stop Register SELR 0x00CA W xxxxxxxx Serial Port E Status Register SESR 0x00CB...

Page 343: ...334 Rabbit 3000 Microprocessor ...

Page 344: ...is perfect Bugs are always present in a system of any size In order to prevent danger to life or property it is the responsibility of the system designer to incorporate redundant protective mechanisms appropriate to the risk involved All Rabbit Semiconductor products are 100 percent functionally tested Additional testing may include visual quality control inspections or mechanical defects analyzer...

Page 345: ......

Page 346: ...clock 12 time date clock 12 timed output pulses 49 timers 15 design standards programming port 18 Dynamic C 1 19 BIOS 237 library functions 242 periodic interrupts 238 power consumption 241 virtual drivers 238 watchdog 238 E EMI mitigation 211 PCB layout 212 spectrum spreader 212 extended memory I and D space 27 28 practical considerations 30 stack segment 29 external bus read and write timing 64 ...

Page 347: ...ts Rabbit slave port 199 slave port lines 203 slave port registers 204 power consumption 85 229 clock 235 236 Dynamic C 241 mechanisms 232 memory 234 sleepy mode 231 233 power management 241 power usage standby mode 210 programming port 269 alternate programming port 270 use as diagnostic port 270 PWM modulator 103 311 PWM outputs 17 50 Q quadrature decoder 110 quadrature encoder inputs 17 R Rabbi...

Page 348: ...stop regis ters 169 serial port status registers 170 SESR 167 SFAR 167 SFCR 167 SFDR 167 SFER 167 SFLR 167 SFSR 167 shadow registers 243 SPCR 130 204 205 SPDxR 204 SPSR 204 206 stack pointer 22 status register 22 STKCR 290 STKHLR 290 STKLLR 290 SWDTR 292 System User mode 319 TACR 151 154 TACSR 151 152 TAPR 151 154 TATxR 151 TBCLR 156 158 TBCMR 156 TBCR 156 157 TBCSR 156 157 TBLxR 156 158 TBMxR 156...

Page 349: ...F synchronous com munication 187 receive serial data timing 181 registers 164 status registers 170 status registers clock serial ports A D 171 transmit serial data timing 180 slave port 53 199 applications 206 hardware design 204 messaging protocol 207 protocols 206 R W cycles 200 registers 204 typical connections 203 sleepy mode 231 233 specifications DC characteristics 68 I O buffer sinking and ...

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