REL1.1
Page 72 of 89
iWave Systems Technologies Pvt. Ltd.
Zynq-Ult MPSoC SOM Development Platform Hardware User Guide
iW-RainboW-G30D-ZynqUltMPSoC SOM DevKit Clock Tree
B
oa
rd
to
B
oa
rd
Con
n
ect
o
r 1
FM
C
Con
n
ect
o
r
1
HS_TXVR1_REFCLK_CH0
REFCLK0
REFCLK1
GBTCLK0_M2C
GBTCLK1_M2C
Clock
Synthesizer
OUT0
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
HS_TXVR4_RX_CH5
HS_TXVR2_RX_CH5
HS_TXVR3_RX_CH5
PCIe_REFCLKP
HS_TXVR1_RX_CH5
HS_TXVR1_REFCLK_CH1
HS_TXVR2_REFCLK_CH1
HS_TXVR3_REFCLK_CH1
HS_TXVR4_REFCLK_CH1
HS_TXVR4_RX_CH5
G
TH
B
an
k
223
REFCLK0
REFCLK1
G
TH
B
an
k
224
B
oa
rd
to
B
oa
rd
Con
n
ect
o
r 2
HS_TXVR3_RX_CH5
HS_TXVR2_RX_CH5
B
oa
rd
to
B
oa
rd
Con
n
ect
o
r 1
PS-REFCLK1
G
TR
B
an
k
505
HS_TXVR1_RX_CH5
PCIe x4
Connector
PCIe_REFCLKP
REFCLK0
REFCLK1
G
TH
B
an
k
225
HS_TXVR3_REFCLK_CH0
HS_TXVR3_REFCLK_CH1
HS_TXVR2_REFCLK_CH0
HS_TXVR1_REFCLK_CH1
HS_TXVR2_REFCLK_CH1
B
oa
rd
to
B
oa
rd
Con
n
ect
o
r 2
FM
C
Con
n
ect
o
r
2
GBTCLK0_M2C
GBTCLK1_M2C
REFCLK1
G
TH
B
an
k
226
HS_TXVR4_REFCLK_CH1
REFCLK0
HS_TXVR4_REFCLK_CH0
HS_TXVR3_REFCLK_CH0
PS-REFCLK0
G
TR
B
an
k
505
G
TR
B
an
k
505
PS-REFCLK2
G
TR
B
an
k
505
PS-REFCLK3
Figure 25: Clock Tree