REL1.1
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iWave Systems Technologies Pvt. Ltd.
Zynq-Ult MPSoC SOM Development Platform Hardware User Guide
2.6.4
GPIO Header
The Zynq Ult MPSoC Carrier board supports GPIO Header (J7) for General Purpose. This Header signals are
directly connected from Board to Board connectors. This header supports I2C0, UART1, SPI0, CAN1 and PS GPIOs. This
GPIO Header (J7) is physically located at the top of the board as shown below.
Figure 27: GPIO Header
Table 17: GPIO Header Pin Assignment
Pin
No
Signal Name
Signal Type/
Termination
Description
1
VCC_1V8
O, 1.8V Power
1V8 Supply Voltage.
2
VCC_5V
O, 5V Power
5V Supply Voltage.
3
CAN1_RX(PS_MIO41_501)
I, 1.8V LVCMOS
CAN1 Receive data. Same pin can be configured as
General Purpose Input/Output if required.
This Pin is connected to 211
th
pin of Board to Board
Connector1 (J10).
4
PS_I2C0_SDA
IO, 1.8V OD/
4.7K PU
I2C0 data.
This Pin is connected to 46
th
pin of Board to Board
Connector2 (J11).