iWave iW-RainboW-G15S, Hardware User'S Manual

Page: 47 / 61

Rev 1.1
Page 47 of 61
i.MX6 Pico ITX - SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
39 GND Power 0V Ground
40 ESAI_HCKR(GPIO_3) Output 3.3V CMOS Media Local Bus single ended
clock line
41 eCSPI2_MISO(CSI0_DAT10) Input 3.3V CMOS SPI Master In Slave Out
42 CSI0_DAT12 Input 3.3V CMOS Camera0 data bit0
43 CSI0_VSYNC Input 3.3V CMOS Camera0 VSYNC
44 CSI0_DAT14 Input 3.3V CMOS Camera0 data bit2
45 eCSPI2_MOSI(CSI0_DAT9 ) Output 3.3V CMOS SPI Master Out Slave In
46 eCSPI2_SS0(CSI0_DAT11) Output 3.3V CMOS SPI chip select 0
47 CSI0_DAT17 Input 3.3V CMOS Camera0 data bit5
48
CSI0_DAT16 Input 3.3V CMOS Camera0 data bit4
49 CSI0_DAT15 Input 3.3V CMOS Camera0 data bit3
50 CSI0_DAT19 Input 3.3V CMOS Camera0 data bit7
51 eCSPI2_SCLK(CSI0_DAT8) Output 3.3V CMOS SPI clock output
52 CSI0_DAT18 Input 3.3V CMOS Camera0 data bit6
53 GND Power 0V Ground
54 GND Power 0V Ground
55 DSI_CLK0P Output Differential MIPI DSI differential clock
positive
56 DSI_CLK0M Output Differential MIPI DSI differential clock
negative
57 DSI_D1P Output Differential MIPI DSI differential data1
positive
58 DSI_D1M Output Differential MIPI DSI differential data1
negative
59 DSI_D0P Output Differential MIPI DSI differential data0
positive
60 DSI_D0M Output Differential MIPI DSI differential
data0negative
61
GND
Power 0V Ground
62 GND Power 0V Ground
63 CLK2_p Output Differential General purpose high speed
differential clock2 positive from
CPU.
64 CLK2_n Output Differential General purpose high speed
differential clock2 negative
from CPU.