IGEPv2 BOARD HARDWARE USER MANUAL v1.20
ISEE 2007 SL. All rights reserved, IGEP® is a registered trademark from ISEE 2007 SL. The following is
provided for informational purposes only.
DOCUMENT FROM ISEE 2007 S.L. MAN-PR-IGEP.0020-001.20.HW_RC 10/1/2010
43
5.6.2
CONNECTOR JA42
Figure 43 IGEPv2 revision B and C JA42 location
Pin# Signal
I/O
Description
1
VIO_1V8
PWR 1.8V buffer reference rail.
2
SYS_BOOT5
I
OMAP boot config
3
DC_5V
PWR 5V reference rail.
4
GND
PWR
5
SYS_BOOT0
I
OMAP boot config
6
SYS_BOOT1
I
OMAP boot config
7
DVI_VSYNC
O
LCD Vertical Sync
8
DVI_HSYNC
O
LCD Horizontal Sync
9
DVI_ACBIAS
O
LCD control
10
DVI_PUP
O
Control signal for the DVI controller. When Hi, DVI is
enabled. Can be used to activate circuitry on adapter board
if desired.
11
DVI_PCLK
O
LCD clock
12
TS_nPEN_IRQ
O
Touchscreen control
13
LCD_QVGA/nVGA O
Touchscreen control
14
TS_ENVVDD
O
Touchscreen control
15
LCD_RESB
O
Touchscreen control
16
LCD_INI
O
Touchscreen control
17
MCSPI1_CLK
O
Touchscreen control
18
MCSPI1_SIMO
I
Touchscreen control
19
MCSPI1_CS0
O
Touchscreen control
20
MCSPI1_SOMI
O
Touchscreen control
Table 3 JA42 connector pinout
The current available on the DC_5V rail is limited to the available current that
remains from the DC supply that is connected to the DC power jack on the board.
Keep in mind that some of that power is needed by the USB Host power rail and if
more power is needed for the expansion board, the main DC power supply current
