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Isee IGEPv2 BOARD, Hardware Reference Manual

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Isee IGEPv2 BOARD Hardware Reference Manual Download Page 10

 IGEPv2 BOARD HARDWARE USER MANUAL v1.20 

 

ISEE 2007 SL. All rights reserved, IGEP® is a registered trademark from ISEE 2007 SL. The following is 
provided for informational purposes only. 

DOCUMENT FROM ISEE 2007 S.L.        MAN-PR-IGEP.0020-001.20.HW_RC                  10/1/2010 

10 

 

 

 

USB 2.0 LS/FS/HS OTG 

On  the  board  a  single  USB  2.0  OTG  Port  is 
provided.  

 

Figure 2 USB OTG connector 

It is not possible to power the board with the OTG connector. 

USB 2.0 HS HOST 

On the board a single USB 2.0 HS HOST only one port is provided via a USB Type A 
socket connector. Hardware provides power on/off switch control and up to 500mA 
of current limit at 5V. 

Figure 3 USB HOST connector 

 

USB  HOST  Port  supports  only  high  speed  devices  (USB  2.0 
HS devices). In order to support low speed devices (USB 1.0 
LS devices) or full speed devices (USB 1.1 FS devices), external USB 2.0 HUB must 
be used. 

WIFI 

IEEE802.11b/g compliant. 

Chipset  based  on  Marvell  88W8686.  The  88W8686  integrates  a  RF  transceiver 
operating  at  2.4GHz,  a  physical  layer,  a  media  access  controller,  and  an  ARM 
processor into a single die. 

BLUETOOTH 

Bluetooth 2.0 compliant.  

Class 2, 2.5 mW (4 dBm) ~10 meters 

Version 2.0 + EDR 3 Mbit/s 

ETHERNET 

A RJ45 connector is provided for the Ethernet Auto-MDIX Full Duplex 10/100 Base T 
interface. 

There is a EEPROM (U830) memory for MAC configuration (Not populated). 

NOTE: Contact ISEE sales for custom assembly boards

.

 

Summary of Contents for IGEPv2 BOARD

Page 1: ...tronics Engineering Address C Vallespir nº19 Planta 1 Modulo 1 Post Code 08224 City Sant Cugat Country SPAIN Phone 34 93 576 39 31 sales iseebcn com http www iseebcn com http www igep es IGEPv2 BOARD Hardware Reference Manual Revision 1 20 1 10 2010 ...

Page 2: ...m 15 3 2 2 IGEPv2 Revision C board series block diagram 16 3 2 3 IGEPv2 Revision C board series improvements 17 3 3 GENERAL VIEW 18 3 3 1 IGEPv2 Revision B board series view 18 3 3 2 IGEPv2 Revision C board series view 19 3 4 MECHANICAL SPECIFICATION 20 3 4 1 IGEPv2 Revision B board series mechanical 20 3 4 2 IGEPv2 Revision C board series mechanical 21 3 5 ELECTRICAL SPECIFICATIONS 22 4 WIFI BLUE...

Page 3: ... J940 POWER RS485 31 5 4 CONNECTOR J960 SERIAL PORT DEBUG EXTRA RS232 33 5 5 CONNECTOR J971 KEYBOARD MATRIX 4x4 37 5 6 TFT CONNECTORS JA41 JA42 39 5 6 1 CONNECTOR JA41 39 5 6 2 CONNECTOR JA42 43 5 6 3 CONNECTOR JA41 JA42 COUNTERPART 44 5 7 CONNECTOR J990 GPIO 45 5 8 IGEPv2 ANTENNAS INTERNAL EXTERNAL UD11 JD21 JD22 50 5 9 CONNECTOR JC20 JC21 ANALOG TO DIGITAL CONVERTER 54 5 10 CONNECTOR JC30 CAMERA...

Page 4: ... DATE ORIGIN DESCRIPTION 1 00 19 03 2009 R D Initial version 1 02 20 05 2009 R D Board Configuration update 1 10 24 07 2009 R D Update Hw Revision RB 1 11 21 09 2009 R D Document Update 1 12 24 09 2009 R D Document Update 1 13 23 10 2009 R D Document Update 1 14 18 11 2009 R D Document Update 1 15 9 03 2010 R D Update Hw Revision RC 1 16 15 05 2010 R D Document Update 1 17 6 07 2010 R D Document U...

Page 5: ...E WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies ISEE 2007 SL from all claims arising from the handling or use of the goods Due to the open con...

Page 6: ...ts or services might be or are used WARRANTY IGEPV2 is warranted against defects in materials and workmanship for a period of 1 year from purchase This warranty does not cover any problems occurring as a result of improper use modifications exposure to water excessive voltages abuse or accidents All boards will be returned via standard mail if an issue is found If no issue is found or express retu...

Page 7: ... DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 7 3 ISEE IGEPV2 BOARD FEATURES Description Characteristics Processor OMAP3530 ARM Cortex A8 Processor Speed 720 Mhz Memory SDRAM 512 MBytes LPDDR SDRAM 200 Mhz Nand Flash 512 Mbytes DSP TMS320DM64 DSP Speed 430 Mhz Video 3D Accelerator PowerVR SGX 530 Power Management TPS65950 Debug Console RS232 JTAG Interface ...

Page 8: ...pported DVI video output DVI D using HDMI connector video and TS lines are available in expansion connector also Power 5Vcc 1A 3 5mm socket connector for wall plug or JST Connector Expansion connector Power 5V and 1 8V UART McBSP McSPI I2C GPIO RS485 with transceiver Keyboard Wifi IEEE 802 11b g 2 4GHz Bluetooth 2 0 Antenna WiFi Bluetooth 1 shared internal antenna integrated on PCB Ethernet 10 100...

Page 9: ...e memory NAND and SDRAM are mounted on top of the OMAP3530 For this reason when looking at the IGEPv2 BOARD you will not find an actual part labeled OMAP3530 Figure 1 POP Package Memory The memory is mounted on top of the processor as mentioned The key function of the POP memory is to provide 4Gb NAND x 16 512MB 4Gb LP DDR SDRAM x32 512MB 200MHz Power Management The TPS65950 is used on the board t...

Page 10: ...d up to 500mA of current limit at 5V Figure 3 USB HOST connector USB HOST Port supports only high speed devices USB 2 0 HS devices In order to support low speed devices USB 1 0 LS devices or full speed devices USB 1 1 FS devices external USB 2 0 HUB must be used WIFI IEEE802 11b g compliant Chipset based on Marvell 88W8686 The 88W8686 integrates a RF transceiver operating at 2 4GHz a physical laye...

Page 11: ...ET connector This connectors comes with link and activity status led Stereo Audio Output Connector A 3 5mm standard stereo output audio jack is provided to access the stereo output of the onboard audio CODEC The Audio CODEC is provided by the TPS65950 Figure 5 Stereo Output connector location Stereo Audio In connector A 3 5mm standard stereo audio input jack is provided to access the stereo input ...

Page 12: ...only The user must use a HDMI to DVI D cable or adapter to connect to a LCD monitor A standard HDMI cable can be used when connecting to a monitor with and HDMI connector LCD and touchscreen header A pair of 1 27mm pitch 2x10 headers are provided to have access to the LCD signals and touchscreen control IGEPv2 Revision B boards On IGEPv2 Revision C boards JA41 connector is wider and enhanced with ...

Page 13: ...v2 Revision B are default populated On IGEPv2 Revision C RS485 are not default populated Contact ISEE sales for custom assembly boards for RS485 feature ANALOG TO DIGITAL CONVERTER A D The IGEPv2 BOARD could come with one ADC Analog to digital converter device The analog signal inputs from U FL HIROSE connector located at the bottom or two 2 54mm pins header Several ADC devices can be populated Fo...

Page 14: ... only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 14 Expansion Header An option for a single 28 pin header is provided on the board to allow for the connection of various expansion cards that could be developed by the users or other sources Due to multiplexing different signals can be provided on each pin providing more that 24 actual signal accesses ...

Page 15: ...010 15 3 2 SYSTEM BLOCK DIAGRAM 3 2 1 IGEPV2 REVISION B BOARD SERIES BLOCK DIAGRAM Figure 8 IGEPv2 Revision B board series block diagram OMAP3530 USB HOST HS microSD INTERFACE JTAG INTERFACE ETHERNET INTERFACE WIFI INTERFACE BLUETOOTH INTERFACE DVI INTERFACE USB OTG LS FS HS TPS65950 STEREO IN STEREO OUT DVI digital transmiter ETHERNET Controller 10 E100 WIFI BLUETOOTH COMBO Controller RS485 INTER...

Page 16: ...REVISION C BOARD SERIES BLOCK DIAGRAM Figure 9 IGEPv2 Revision C board series block diagram OMAP3530 USB HOST HS microSD INTERFACE JTAG INTERFACE ETHERNET INTERFACE WIFI INTERFACE BLUETOOTH INTERFACE DVI INTERFACE USB OTG LS FS HS TPS65950 STEREO IN STEREO OUT DVI digital transmiter ETHERNET Controller 10 E100 WIFI BLUETOOTH COMBO Controller RS485 INTERFACE RS485 DRIVER EXPANSION INTERFACE RS232 D...

Page 17: ...ctor Optional high speed 3MBps ADC Hirose U FL connector or two pin header Added second RS232 UART on J960 Now 2 UARTs on J960 UART3 UART1 Changed JD22 from GSC Murata connector to Hirose U FL connector Added optional second external antenna Hirose U FL connector New GPIO to physically reset BT module Added resistors for hardware UART selection Non populated parts o J400 JTAG connector o J990 GPIO...

Page 18: ...ISEE 2007 SL The following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 18 3 3 GENERAL VIEW 3 3 1 IGEPV2 REVISION B BOARD SERIES VIEW Figure 10 IGEPv2 revision B board top side components Figure 11 IGEPv2 revision B board bottom side components ...

Page 19: ...rk from ISEE 2007 SL The following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 19 3 3 2 IGEPV2 REVISION C BOARD SERIES VIEW Figure 12 IGEPv2 revision C board top side components Figure 13 IGEPv2 revision C board bottom side components ...

Page 20: ... provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 20 3 4 MECHANICAL SPECIFICATION 3 4 1 IGEPV2 REVISION B BOARD SERIES MECHANICAL Figure 14 IGEPv2 RB Top view mechanical specification Get Mechanical drawings on http www igep es User Menu Download 01 Products IGEPv2 HW_Mechanical ...

Page 21: ...he following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 21 3 4 2 IGEPV2 REVISION C BOARD SERIES MECHANICAL Figure 15 IGEPv2 RC Top view mechanical specification Get Mechanical drawings on http www igep es User Menu Download 01 Products IGEPv2 HW_Mechanical ...

Page 22: ...igh 2 8 V Output Voltage Low 0 4 V Input Resistance 12 15 KOhms JTAG Realview ICE Tool 30 MHz XDS560 30 MHz XDS510 30 MHz Lauterbach tm 30 MHz microSD Voltage Mode 1 8V 1 71 1 8 1 89 Voltage Mode 3 3V 3 2 3 3 Current 220 mA Clock 48 MHz DVI D Pixel Clock Frequency 25 75 MHZ High level output voltage 3 3 V Swing output voltage 400 600 mVp p Maximum resolution 67 5 75 82 5 Ohms Audio In Peak to peak...

Page 23: ...wer Levels 15 5 17 5 19 5 dBm Minimum Input Level Sensitivity 11Mbps FER 8 87 81 dBm Maximum Input Level 10 5 dBm Wifi IEEE802 11g Specification IEEE802 11g Frequency 2400 2500MHz 2400 2483 5 MHz Data rate 6 9 12 18 24 36 48 54 Mbps Power Levels 13 14 8 17 0 dBm Minimum Input Level Sensitivity 11Mbps FER 8 71 65 dBm Maximum Input Level 20 15 dBm Bluetooth 2 0 Bluetooth specification 2 0 Channel sp...

Page 24: ...sor into a single die BLUETOOTH Chipset based on CSR BC4ROM 21e 4 1 BLOCK DIAGRAM Figure 16 Wifi Bluetooth Combo module block Diagram 4 2 INTERFACES Terminal Name Type System Description RST_N_B I BT Reset active low It must be low for 5ms PCM_OUT O BT Synchronous data output CMOS output tri statable with weak internal pull down PCM_SYNC I O BT Synchronous data sync Bi Directional with weak intern...

Page 25: ...t Mode SD_DAT 2 Read Wait optional SDIO SPI Model SD_DAT 2 Reserved SD_D1 SPI_SDO I O WLAN G SPI Mode SPI_SDO G SPI Data Output SDIO 4 bit Mode SD_DAT 1 Data Line Bit 1 SDIO 1 bit Mode SD_DAT 1 Interrupt SDIO SPI Model SD_DAT 1 Reserved SD_D0 SPI_SCSn I O WLAN G SPI Mode SPI_SCSn G SPI Chip Select input SDIO 4 bit Mode SD_DAT 0 Data Line Bit 0 SDIO 1 bit Mode SD_DAT 0 Data Line SDIO SPI Model SD_D...

Page 26: ...EP 0020 001 20 HW_RC 10 1 2010 26 PDn pin separated from RESET_N_W Host controls pulsing of RESET_N_W pin 4 4 WLAN RESET PDN PINS Reset can be done by using GPIO_94 or GPIO_138 By default RD41 is mounted Power down can be done by using GPIO_95 or GPIO_139 By default RD43 is mounted 4 5 BLUETOOTH RESET PINS Reset can be done by using GPIO182 or GPIO137 By default RD137 is mounted 4 6 PCM INTERFACE ...

Page 27: ... ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 27 4 6 2 WIFI MODULE SIDE PCM_OUT Output Synchronous data output CMOS output tri state with weak internal pull down PCM_SYNC I O Synchronous data sync Bi Directional with weak internal pull down PCM_IN Input Synchronous data input CMOS input with weak pull down PCM_CLK I O Synchronous data clock Bi Directional with weak internal pull down ...

Page 28: ... JTAG DEBUG Connector J940 Power RS485 Connector J960 UART3 Serial Debug Only IGEPv2 Revision C has also UART1 on J960 Connector J971 Keyboard Matrix 4x4 Connector JA41 JA42 External TFT interface 18 bits Only IGEPv2 Revision C more TFT depth 24 bits Connector J990 GPIO muxed with UART2 MMC2 McBSP3 McSPI I2C Connector JD22 Optional external Wifi bluetooth Antenna IGEPv2 boards come with a default ...

Page 29: ...0 MAIN 5 0VCC POWER The J200 connector is a power jack for main 5 VDC power It is a RASM722 switchcraft connector Plug Mating Plug Diameter 2 1mm ID 5 5mm OD Figure 17 J200 detail WARNING IGEPv2 BOARD CAN ONLY BE POWERED WITH 5V DC POWER SUPPLY OR THE BOARD WILL BE DAMAGED 5 2 CONNECTOR J400 JTAG DEBUG The J400 connector is a 14 pins 2x7 dual row 2 54mm Figure 18 J400 detail Pins 1 2 13 and 14 are...

Page 30: ...FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 30 Figure 19 J400 location The schematic below illustrate the pinout of the connector Figure 20 Schematic J400 WARNING The JTAG signals go directly to OMAP processor Improperly use of this connector could result in damage of the processor Note ISEE recommend JTAG Debugger XDS510 USB from Spectrum Digital with Code Composer Studio ...

Page 31: ...5 The J940 connector is a HEADER CONNECTOR PH SIDE 5POS 2MM SMD from JST Part Number S5B PH SM3 TB It matches to JST CONNECTOR HOUSING PH 5POS 2MM WHITE Part Number JST PHR 5 and JST TERMINALS CRIMP PH 24 30AWG Part Number JST SPH 002T P0 5S IGEPv2 don t include cable neither plug connector Pin 1 is labeled on the PCB The connector is located as shows the figure below Figure 21 J940 location Figur...

Page 32: ...RC 10 1 2010 32 Figure 23 Schematic J940 User can use this connector to power the board with 5VDC Use only 5V regulated DC The IGEPv2 BOARD does not use this 9v power supply Only on IGEPv2 revision B the PWR_9V input is directly routed to JC01 and J971 connectors On IGEPv2 revision C is not available There is also a RS485 transceiver on the connector Figure 24 Schematic RS485 driver Figure 25 Sche...

Page 33: ... following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 33 5 4 CONNECTOR J960 SERIAL PORT DEBUG EXTRA RS232 The J960 connector is a 5x2 pins double row 2 54mm Figure 26 J960 detail The connector is located as shows the figure below Figure 27 J960 location Pin1 ...

Page 34: ...ebug RS232 interface with RS232 transceiver Figure 28 IGEPv2 revision B schematic J960 On IGEPv2 revision C several features have been added NOTE Contact ISEE sales for custom assembly boards Additional RS232 port UART1 on same J960 connector It is only needed to rotate 180º the IDC 10 AT Everex to DB9 cable It has been added resistors for alternative UART1 UART2 and UART3 hardware selection Also ...

Page 35: ... ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 35 The schematic below illustrate IGEPv2 revision C pin out of the connector Figure 29 IGEPv2 revision C Schematic J960 First RS232 is located on J960 pins 2 and 3 and the second one on pins 8 and 9 Next resistors enable hardware UART select to assign them on each connector Figure 30 IGEPv2 revision C resistors for UART hardware selection ...

Page 36: ...ational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 36 The 5x2 Header follow the IDC 10 AT Everex configuration Figure 31 IDC 10 to DB9 cable So it is needed null modem configuration direct connection between two computers RX and TX lines are crossed in this null modem configuration between two equipments TX1 RX2 TX2 RX1 ...

Page 37: ...M ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 37 5 5 CONNECTOR J971 KEYBOARD MATRIX 4X4 The J971 connector is an 8 pins single row 2 54mm It is not default populated on IGEPv2 boards Figure 32 J971 detail Its can be used to connect a 4x4 keyboard matrix Figure 33 Keyboard matrix 4x4 and schematic example Pin 1 is labeled on the PCB The connector is located as shows the figure below ...

Page 38: ...elow illustrate the pin out of the connector Figure 35 Schematic J971 KPD_Cx columns KPD_Rx rows When a key button of the keyboard matrix is pressed the corresponding row and column lines are shorted together To allow key press detection all input pins KBR are pulled up to VCC and all output pins KBC driven to a low level Any action on a button generates an interrupt to the sequencer The decoding ...

Page 39: ...es only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 39 5 6 TFT CONNECTORS JA41 JA42 There are two 1 27mm Double Row Terminal Strip for the TFT interface Both are from SAMTEC manufacturer Part Number FTS 110 01 L D 5 6 1 CONNECTOR JA41 On IGEPv2 revision B series Figure 36 IGEPv2 revision B JA41 location Figure 37 IGEPv2 revision B JA41 JA42 detail ...

Page 40: ...SEE 2007 SL The following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 40 Figure 38 JA41 JA42 IGEPv2 revision B pinout detail On IGEPv2 revision C series Figure 39 IGEPv2 revision C JA41 location Figure 40 IGEPv2 revision C JA41 and JA42 detail ...

Page 41: ...a bit 8 DVI_DATA5 O LCD Pixel Data bit 9 DVI_DATA6 O LCD Pixel Data bit 10 DVI_DATA7 O LCD Pixel Data bit 11 DVI_DATA8 O LCD Pixel Data bit 12 DVI_DATA9 O LCD Pixel Data bit 13 DVI_DATA10 O LCD Pixel Data bit 14 DVI_DATA11 O LCD Pixel Data bit 15 DVI_DATA12 O LCD Pixel Data bit 16 DVI_DATA13 O LCD Pixel Data bit 17 DVI_DATA14 O LCD Pixel Data bit 18 DVI_DATA15 O LCD Pixel Data bit 19 DVI_DATA16 O ...

Page 42: ...TA4 UART3_RX GPIO74 DVI_DATA5 DATA5 UART3_TX GPIO75 DVI_DATA6 DATA6 UART1_TX GPIO_76 DVI_DATA7 DATA7 UART1_RX GPIO_77 DVI_DATA8 DATA8 GPIO_78 DVI_DATA9 DATA9 GPIO_79 DVI_DATA10 DATA10 GPIO79 DVI_DATA11 DATA11 GPIO81 DVI_DATA12 DATA12 GPIO82 DVI_DATA13 DATA13 GPIO83 DVI_DATA14 DATA14 GPIO84 DVI_DATA15 DATA15 GPIO85 DVI_DATA16 DATA16 GPIO86 DVI_DATA17 DATA17 GPIO87 DVI_DATA18 DATA18 GPIO88 DVI_DATA1...

Page 43: ...UP O Control signal for the DVI controller When Hi DVI is enabled Can be used to activate circuitry on adapter board if desired 11 DVI_PCLK O LCD clock 12 TS_nPEN_IRQ O Touchscreen control 13 LCD_QVGA nVGA O Touchscreen control 14 TS_ENVVDD O Touchscreen control 15 LCD_RESB O Touchscreen control 16 LCD_INI O Touchscreen control 17 MCSPI1_CLK O Touchscreen control 18 MCSPI1_SIMO I Touchscreen contr...

Page 44: ...power circuitry on the board The 3 3V rail also has limited capacity on the power as well It is suggested that the 5V rail be used to generate the required voltages for an adapter card Figure 44 IGEPv2 revision B and C Schematic JA42 NOTE JA41 and JA42 connectors are NOT BeagleBoard compatible WARNING The TFT signals goes directly to OMAP processor Improperly use of this connector could result in ...

Page 45: ... is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 45 5 7 CONNECTOR J990 GPIO The J990 connector is a 28 pins 2x14 dual row 2 54mm Figure 45 J990 detail Pins 1 2 27 and 28 are labeled on PCB Figure 46 J990 location The schematic below illustrate the pin out of the connectors ...

Page 46: ...0 connector is BeagleBoard compatible expansion connector http beagleboard org IGEPv2 NOWIFI board is fully compatible Other IGEPv2 board versions need software configuration to disable wifi interface and others because of shared hardware lines MMC2 interface is used by wifi module McBSP3 interface is used by PCM TPS65950 interface Pin MUX 0 MUX 1 MUX 2 MUX 4 1 VIO_1V8 2 DC_5V 3 MMC2_DAT7 GPIO_139...

Page 47: ...C2_DAT7 SD MMC data pin 7 I O 3 MMC2_DAT6 SD MMC data pin 6 I O 5 MMC2_DAT5 SD MMC data pin 5 I O 7 MMC2_DAT4 SD MMC data pin 4 I O 9 MMC2_DAT3 SD MMC data pin 3 I O 11 MMC2_DAT2 SD MMC data pin 2 I O 13 MMC2_DAT1 SD MMC data pin 1 I O 15 MMC2_DAT0 SD MMC data pin 0 I O 17 MMC2_CMD SD MMC command signal I O 19 MMC_CLKO SD MMC clock signal O 21 McBSP Port 1 McBSP1_DR Multi channel buffered serial p...

Page 48: ...an interrupt pin I O 4 GPIO_141 General Purpose Input Output pin Can be used as an interrupt pin I O 10 GPIO_142 General Purpose Input Output pin Can be used as an interrupt pin I O 6 GPIO_143 General Purpose Input Output pin Can be used as an interrupt pin I O 8 GPIO_156 General Purpose Input Output pin Can be used as an interrupt pin I O 20 GPIO_158 General Purpose Input Output pin Can be used a...

Page 49: ...T request to send O 10 UART2_RX UART receive I 8 UART2_TX UART transmit O 6 GPT_PWM GPT9_PWMEVT PWM or event for GP timer O 4 GPT11_PWMEVT PWM or event for GP timer O 10 GPT10_PWMEVT PWM or event for GP timer O 8 Table 5 Expansion Connector signals WARNING The GPIO signals go directly to OMAP processor Improperly use of this connector could result in damage of the processor J990 mates with SAMTEC ...

Page 50: ...HW_RC 10 1 2010 50 5 8 IGEPv2 ANTENNAS INTERNAL EXTERNAL UD11 JD21 JD22 On IGEPv2 revision B series JD11 is a GSC connector for the external WIFI interface It is a MURATA GSC connector Part number MM9329 2700RA1 Figure 50 IGEPv2 revision B JD11 location For the cable you will find cable assemblies if you look for CABLE ASSEMBLY RF GSM MURATA to SMA MALE Figure 49 IGEPv2 revision B JD11 detail Figu...

Page 51: ...ovided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 51 On IGEPv2 revision C series JD21 and JD22 are U FL series HIROSE connector for the external WIFI BLUETOOTH antenna Part number U FL R SMT 1 Figure 51 U FL series receptacle connector specification Figure 52 U FL serie Mated connector ...

Page 52: ...iguration for IGEPv2 revision C UD11 LD30 1 8nH LD31 1 5nH CD31 15pF are populated JD21 JD22 CD32 and CD33 are not populated OPTION 2 An external shared antenna for both BT and WIFI interfaces JD22 is populated JD21 UD11 LD30 LD31 CD31 CD32 and CD33 are not populated OPTION 3 Two external antennas for each BT and WIFI interfaces This configuration is not available yet on wifi combo module JD21 JD2...

Page 53: ...ovided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 53 NOTE Contact ISEE sales for custom assembly boards Figure 54 IGEPv2 revision C antenna schematic Figure 55 IGEPv2 revision C JD21 JD22 location JD22 on yellow box up JD21 on blue box down Figure 56 IGEPv2 revision C JD21 JD22 detail ...

Page 54: ...R IGEP 0020 001 20 HW_RC 10 1 2010 54 5 9 CONNECTOR JC20 JC21 ANALOG TO DIGITAL CONVERTER JC20 is a U FL serie HIROSE connector for the analog to digital converter input Part number U FL R SMT 1 On IGEPv2 Revision C analog to digital converter are not default populated Contact ISEE sales for custom assembly boards for this feature Figure 57 IGEPv2 revision C JC20 location Figure 58 IGEPv2 revision...

Page 55: ...IGEP is a registered trademark from ISEE 2007 SL The following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 55 Figure 59 IGEPv2 revision C schematic A D Figure 60 IGEPv2 revision C schematic A D SPI interface ...

Page 56: ...30 CAMERA CONNECTOR There is one 1 27mm Double Row Terminal Strip for the Camera interface from from SAMTEC manufacturer Part Number FTS 114 01 L D This JC30 connector is only available on IGEPv2 revision C series Figure 61 IGEPv2 revision C JC30 location Figure 62 IGEPv2 revision C JC30 detail Figure 63 IGEPv2 revision C JC30 pinout detail These connectors allow the access to the Camera interface...

Page 57: ...CAM_D9 I Camera interface 19 CAM_XCLKB I Camera interface 20 CAM_D11 Camera interface 21 GPIO_112 I2C2_SCL I2C interface 22 GPIO_113 I2C2_SDA I2C interface 23 CAM_RESET Camera interface 24 CAM_PDN Camera interface 25 CAM_STROBE Camera interface 26 CAM_WEN Camera interface 27 3V3 PWR 28 3V3 PWR Table 6 IGEPv2 revision C JC30 connector pinout This connector can also be used for other functions on th...

Page 58: ...O111 CAM_PCLK CAM_PCLK GPIO97 CAM_FLD CAM_FLD GPIO98 CAM_WEN CAM_WEN GPIO167 CAM_STROBE CAM_STROBE GPIO126 Table 7 IGEPv2 revision C JC30 connector mux All signals are 1 8V It is suggested that the 3V3 rail be used to generate the required voltages for an adapter card The schematic below illustrate the pin out of the connectors Figure 64 IGEPv2 revision C JC30 schematic WARNING The CAMERA signals ...

Page 59: ...s only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 59 5 11S_VIDEO SIGNALS TP400 and TP401 S video signals are available on TP400 and TP401 test points Figure 65 TP400 and TP401 schematic Figure 66 TP400 and TP401 location WARNING The VIDEO signals go directly to OMAP processor Improperly use of this connector could result in damage of the processor ...

Page 60: ... be recharged from the main battery This RTC feature is only available on IGEPv2 revision C series When the main battery is below 2 7 V or is removed the backup battery powers the backup if the backup battery voltage is greater than 1 8 V The backup domain powers up the following Internal 32 768 kHz oscillator and RTC Hash table 20 registers of 8 bits each and Eight GP storage registers TPS65950 b...

Page 61: ... a registered trademark from ISEE 2007 SL The following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 61 C741 is an Electric Double Layer Capacitors from PANASONIC Serie EN Figure 69 IGEPv2 revision C BT741 location ...

Page 62: ...ered trademark from ISEE 2007 SL The following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 62 Figure 70 IGEPv2 revision C C741 location ATTENTION If battery is needed resistor R741 must be unmounted Figure 71 R741 location ...

Page 63: ...The following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 63 6 BOARD REFERENCE How is IGEPv2 designed Product Name IGEP0020 RC1 Revision ID RA RB RC Rx x revision family Revision Number 1 2 3 n ID revision This manual is for Boards designed as IGEP0020 RC1 ...

Page 64: ...ion B board series block diagram 15 Figure 9 IGEPv2 Revision C board series block diagram 16 Figure 10 IGEPv2 revision B board top side components 18 Figure 11 IGEPv2 revision B board bottom side components 18 Figure 12 IGEPv2 revision C board top side components 19 Figure 13 IGEPv2 revision C board bottom side components 19 Figure 14 IGEPv2 RB Top view mechanical specification 20 Figure 15 IGEPv2...

Page 65: ...x 4x4 and schematic example 37 Figure 34 J971 location 38 Figure 35 Schematic J971 38 Figure 36 IGEPv2 revision B JA41 location 39 Figure 37 IGEPv2 revision B JA41 JA42 detail 39 Figure 38 JA41 JA42 IGEPv2 revision B pinout detail 40 Figure 39 IGEPv2 revision C JA41 location 40 Figure 40 IGEPv2 revision C JA41 and JA42 detail 40 Figure 41 IGEPv2 revision C JA41 JA42 pinout detail 41 Figure 42 IGEP...

Page 66: ...etail 53 Figure 57 IGEPv2 revision C JC20 location 54 Figure 58 IGEPv2 revision C JC20 detail 54 Figure 59 IGEPv2 revision C schematic A D 55 Figure 60 IGEPv2 revision C schematic A D SPI interface 55 Figure 61 IGEPv2 revision C JC30 location 56 Figure 62 IGEPv2 revision C JC30 detail 56 Figure 63 IGEPv2 revision C JC30 pinout detail 56 Figure 64 IGEPv2 revision C JC30 schematic 58 Figure 65 TP400...

Page 67: ... Mux table on J990 GPIO Chapter 5 7 CONNECTOR J990 GPIO Mux table on JA41 42 TFT Revision 1 12 IGEP 0020 RBx Corrections on mux table on J990 GPIO Chapter 5 7 CONNECTOR J990 GPIO Revision 1 13 IGEP 0020 RBx Note it is not possible to power the board with the OTG connector Add new chapter S_VIDEO SIGNALS Add new chapter BATTERY BACKUP IGEPv2 board warranty 1 year Revision 1 14 IGEP 0020 RBx Add com...

Page 68: ...IGEP is a registered trademark from ISEE 2007 SL The following is provided for informational purposes only DOCUMENT FROM ISEE 2007 S L MAN PR IGEP 0020 001 20 HW_RC 10 1 2010 68 External shared antenna configuration for both BT and WIFI interfaces chapter 5 8 IGEPV2 ANTENNAS ...

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