IGEPv2 BOARD HARDWARE USER MANUAL v1.20
ISEE 2007 SL. All rights reserved, IGEP® is a registered trademark from ISEE 2007 SL. The following is
provided for informational purposes only.
DOCUMENT FROM ISEE 2007 S.L. MAN-PR-IGEP.0020-001.20.HW_RC 10/1/2010
41
Figure 41 IGEPv2 revision C JA41-JA42 pinout detail
These connectors allow the access to the LCD signals. Next table shows the signals
that are on the JA41 and JA42 connector (
shadowed cells are only available on
IGEPv2 revision C series
).
Pin# Signal
I/O
Description
1
3V3
PWR DC rail from the Main DC supply
2
GND
PWR Ground
3
DVI_DATA0
O
LCD Pixel Data bit
4
DVI_DATA1
O
LCD Pixel Data bit
5
DVI_DATA2
O
LCD Pixel Data bit
6
DVI_DATA3
O
LCD Pixel Data bit
7
DVI_DATA4
O
LCD Pixel Data bit
8
DVI_DATA5
O
LCD Pixel Data bit
9
DVI_DATA6
O
LCD Pixel Data bit
10
DVI_DATA7
O
LCD Pixel Data bit
11
DVI_DATA8
O
LCD Pixel Data bit
12
DVI_DATA9
O
LCD Pixel Data bit
13
DVI_DATA10 O
LCD Pixel Data bit
14
DVI_DATA11 O
LCD Pixel Data bit
15
DVI_DATA12 O
LCD Pixel Data bit
16
DVI_DATA13 O
LCD Pixel Data bit
17
DVI_DATA14 O
LCD Pixel Data bit
18
DVI_DATA15 O
LCD Pixel Data bit
19
DVI_DATA16 O
LCD Pixel Data bit
20
DVI_DATA17 O
LCD Pixel Data bit
21
DVI_DATA18 O
LCD Pixel Data bit
22
DVI_DATA19 O
LCD Pixel Data bit
23
DVI_DATA20 O
LCD Pixel Data bit
24
DVI_DATA21 O
LCD Pixel Data bit
25
DVI_DATA22 O
LCD Pixel Data bit
26
DVI_DATA23 O
LCD Pixel Data bit
27
I2C3_SCL
I/O
I2C3 interface
28
I2C3_SDA
I/O
I2C3 interface
Table 1 IGEPv2 revision B and C JA41 connector pinout
This connector can also be used for other functions on the board based on the
multiplexer setting of each pin. Next table shows the options. The MUX: column
