Intrinsyc Open-
Q™ 605 SBC User Guide and HW Specification
V. 1.4
30
Copyright Intrinsyc Technologies Corporation
Due to the nature of Qualcomm Low Power Island (LPI) architecture, changing LPI_GPIOs to an alternate function requires access to
Qualcomm proprietary source code. Please contact Intrinsyc to make changes if an alternate function is needed.
Table 3-14 – Summary of LPI_GPIOs
PIN
#
Signal
Default Function
Description
Alternate
Functions
Description
45
LPI_MI2S_2_SCK
QCS605:
LPI_MI2S_2_SCK
(LPI_GPIO_8)
LPI MI2S 2 bit clock
LPI_QUP_L0(2)
LPI QUP 2, lane 0: UART_CTS
LPI QUP 2, lane 0: SPI_MISO
LPI QUP 2, lane 0: I2C_SDA
47
LPI_MI2S_2_WS
QCS605:
LPI_MI2S_2_WS
(LPI_GPIO_9)
LPI MI2S 2 word select
LPI_QUP_L1(2)
LPI QUP 2, lane 1: UART_RFR
LPI QUP 2, lane 1: SPI_MOSI
LPI QUP 2, lane 1: I2C_SCL
51
LPI_MI2S_2_DATA0
QCS605:
LPI_MI2S_2_DATA
0
(LPI_GPIO_10)
LPI MI2S 2 serial data
channel 0
LPI_QUP_L2(2)
LPI QUP 2, lane 2: UART_TX
LPI QUP 2, lane 2: SPI_SCLK
49
LPI_MI2S_2_DATA1
QCS605:
LPI_MI2S_2_DATA
1 (LPI_GPIO_11)
LPI MI2S 2 serial data
channel 1
LPI_QUP_L3(2)
LPI QUP 2, lane 3: UART_RX
LPI QUP 2, lane 3: SPI_CS0
57
LPI_QUP0_SDA
QCS605:
LPI_QUP_L0(0)
(LPI_GPIO_0)
LPI QUP 0, lane 0: I2C_SDA
SYNC_OUT
LPI_QUP_L0(0)
32 kHz clock output for
synchronization
LPI QUP 0, lane 0: UART_CTS
LPI QUP 0, lane 0: SPI_MISO
59
LPI_QUP0_SCL
QCS605:
LPI_QUP_L1(0)
(LPI_GPIO_1)
LPI QUP 0, lane 1: I2C_SCL
LPI_QUP_L1(0)
LPI QUP 0, lane 1: UART_RFR
LPI QUP 0, lane 1: SPI_MOSI
68
LPI_QUP1_MISO
QCS605:
LPI_QUP_L0(1)
(LPIO_GPIO_2)
LPI QUP 1, lane 0: SPI_MISO LPI_QUP_L0(1)
LPI QUP 1, lane 0: UART_CTS LPI
QUP 1, lane 0: I2C_SDA
64
LPI_QUP1_MOSI
QCS605:
LPI_QUP_L1(1)
(LPI_GPIO_3)
LPI QUP 1, lane 1: SPI_MOSI LPI_QUP_L1(1)
LPI QUP 1, lane 1: UART_RFR LPI
QUP 1, lane 1: I2C_SCL
66
LPI_QUP1_CLK
QCS605:
LPI_QUP_L2(1)
(LPI_GPIO_4)
LPI QUP 1 lane 2: SPI_SCLK
LPI_QUP_L2(1)
LPI QUP 1 lane 2: UART_TX
