Intrinsyc Open-
Q™ 605 SBC User Guide and HW Specification
V. 1.4
29
Copyright Intrinsyc Technologies Corporation
PIN
#
Signal
Default Function
Description
Alternate
Functions
Description
QDSS
QDSS_TRACEDATA_14A QDSS trace data bit 14A
32
GP44_QUP3_L3
QCS605:
QUP_L3(3)
(GPIO_44)
Configurable I/O :
QUP 3, lane 3:
UART_RX
QUP_L3(3)
QDSS_TRACEDATA_15A
Configurable I/O :
QUP 3, lane 3: SPI_CS0
QDSS trace data bit 15 A
37
APQ_GP117
QCS605: GPIO
(GPIO_117)
GPIO
QDSS_TRACEDATA_0A
QDSS trace data bit 0 A
35
APQ_GP118
QCS605: GPIO
(GPIO_118)
GPIO
QDSS_TRACEDATA_1A
QDSS trace data bit 1 A
58
APQ_GP119
QCS605: GPIO
(GPIO_119)
GPIO
QDSS_TRACEDATA_2A
QDSS trace data bit 2 A
41
APQ_GP120
QCS605: GPIO
(GPIO_120)
GPIO
QDSS_TRACEDATA_3A
QDSS trace data bit 3 A
72
GP65_QUP8_L0
QCS605:
QUP_L0(8)
(GPIO_65)
Configurable I/O :
QUP 8, lane 0:
UART_CTS
QUP_L1(8)
MI2S_1_SCK
SWR_CLK
Configurable I/O :
QUP 8, lane 0: I2C_SDA
QUP 8, lane 0: SPI_MISO
MI2S 1bit clock
SoundWire clock
76
GP66_QUP8_L1
QCS605:
QUP_L1(8)
(GPIO_66)
Configurable I/O :
QUP 8, lane 1:
UART_RFR
QUP_L1(8)
MI2S_1_WS
GP_PDM_1A
SWR_DATA
Configurable I/O :
QUP 8, lane 1: I2C_SCL
QUP 8, lane 1: SPI_MOSI
MI2S 1 word select
General-purpose PDM output 1 A
SoundWire data
74
GP67_QUP8_L2
QCS605:
QUP_L2(8)
(GPIO_67)
Configurable I/O :
QUP 8, lane 2:
UART_TX
QUP_L1(8)
MI2S_1_DATA0
Configurable I/O :
QUP 8, lane 2: SPI_SCLK
MI2S 1 data channel 0
70
GP68_QUP8_L3
QCS605:
QUP_L3(8)
(GPIO_68)
Configurable I/O :
QUP 8, lane 3:
UART_RX
QUP_L1(8)
MI2S_1_DATA1
Configurable I/O :
QUP 8, lane 3: SPI_CS0
MI2S 1 data channel 1
