Signal
Name
I/O
Type
Default
Mode
Ball
Coun
t
Default
Direction
and Logic
State
Power
Well
Internal/
External
Resistor Pull-
Up/Down
Description
GPIO60
I/O
Native
1
I
SUS
General Purpose I/O Port 60. Not
Multiplexed.
3
SUS_STAT
#/
GPIO61
I/O
SUS_ST
AT#
1
O (High)
SUS
Suspend Status: This signal is asserted
by the PCH to indicate that the system
will be entering a low power state soon.
This can be monitored by devices with
memory that need to switch from normal
refresh to suspend refresh mode. It can
also be used by other peripherals as an
indication that they should isolate their
outputs that may be going to powered-
off planes.
If SUS_STAT# interface is not used, this
signal can be used as a GPIO Port 61.
SUS_CLK/
GPIO62
I/O
SUS_CL
K
1
O (Low)
SUS
Suspend Clock. This clock is an output of
the RTC generator circuit. It is used by
other chips for refresh clock.
If SUS_CLK interface is not used, the
signals can be used as GPIO Port 62.
SLP_S5#/
GPIO63
I/O
SLP_S5
#
1
O (High)
SUS
S5 Sleep Control. SLP_S5# is for power
plane control. This signal is used to shut
power off to all non-critical systems when
in the S5 (Soft Off) states.
If SLP_S5# interface is not used, the
signals can be used as GPIO Port 63.
GPIO72
4
I/O
Native
1
I
SUS
General Purpose I/O Port 72. Not
Multiplexed.
3
GPIO73
I/O
Native
1
I
SUS
General Purpose I/O Port 73. Not
Multiplexed.
3
SML1ALER
T#/
GPIO74
2
I/O
SML1AL
ERT#
1
I
SUS
When SMBUS:
External pull-up
required
System Management Link Alert 1. This
signal can be connected to an external
BMC. External pull-up resistor to
VCCSUS3P3 is required.
Resistor value should be calculated based
on the bus load, refer to the Platform
Design Guide.
If SML1ALERT# interface is not used, the
signals can be used as GPIO Port 74.
SML1DAT/
GPIO75
2
I/O
SML1DA
T
1
I
SUS
When SMBUS:
External pull-up
required
System Management Link 1 Data. SMBus
link to external BMC.
External pull-up required to VCCSUS3P3
is required.
Resistor value should be calculated based
on the bus load, refer to the Platform
Design Guide.
If SML1DAT interface is not used, the
signals can be used as GPIO Port 75.
TOTAL
67
1. When this signal is configured as GPO, the output stage is an open drain.
2. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the signal is stable in its inactive
state of the native functionality, immediately after reset until it is initialized to GPIO functionality. Multiplexed signals is
visible or Intel reserved.
Technical Reference—Crystal Forest
Intel
®
Xeon
®
Processor E3-1125C with Intel
®
Communications Chipset 8910 Development Kit
October 2012
User Guide
Order No.: 328009-001US
51
