Intel Xeon E3-1125C User Manual Download

Page: 14 / 67

Ref Des

Location

Description

B1B1

Battery

3 V Lithium CR2032 coin battery for real time clock (RTC)

and CMOS memory backup

U9A1

RS232 Transceiver

Two 28-pin connectors to handle all modem control signals

U9A2

1.10

On-Board I/O Connectors

Table 5.

On-Board I/O Connectors

Ref Des Location

Description

J1D1, J1D2

PHY Card Connector

HMZD connector for PHY add-in card

J1G1

Serial ATA Port 0

Two SATA 2 interface connectors. SATA ports 4 and 5 are

referenced as SATA ports 0 and 1 respectively.

J1F6

Serial ATA Port 1

J1E3

USB Port 4 and 5 Header

10-pin (pin 9 is omitted as a plug-in key), dual-row

header that routes two USB ports to an external USB

connector. In conjunction with the rear panel USB ports

there are a total of six USB ports.

J1A7

Front Panel Header

10-pin (pin 10 is omitted as a plug-in key), dual-row

header that provides connection for:
• Power Switch
• Reset Switch
• Power-on LED
• HD Status LED

J8D1

CPU Fan Header

Four-wire CPU fan header.

J3J1

PCH Fan Header

Three-wire PCH fan header.

J5B3

AUX Fan Header

Three-wire header with no fan speed control.

J1H2

LPC Header

20-pin card header for the TPM / LPC bus.

J1J1

LCD Data

16-pin header, not populated, for LCD port 80 output

J2J2

PCH In-Circuit SPI

Programming Header

10-pin header for use with DediProg* SF100 in-circuit

program tool. Used to update PCH SPI device without

removing it from its socket.

J5A1

XDP0 Connector CPU

Top-side 60-pin connector for ITP-XDP processor debug.

XDP is the Extended Debug Port used for component

debugging and testing.

J6D2

XDP1 Connector PCH

Top-side 60-pin connector for the ITP-XDP PCH debug.

XDP is the Extended Debug Port used for component

debugging and testing.

1.11

Expansion I/O Slots

Table 6.

Expansion I/O Slots

Ref Des

Location

Description

Notes

J5B1

PCI Express* Slot

Processor

The PCI Express ports comply with PCI

Express* Base Specification, Rev. 2.0a.

continued...

Crystal Forest—Introduction

Intel

Xeon

Processor E3-1125C with Intel

Communications Chipset 8910 Development Kit

User Guide

October 2012

Order No.: 328009-001US

Summary of Contents for Xeon E3-1125C

Page 1: ...Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 Order No 328009 001US ...

Page 2: ...ations and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not ...

Page 3: ...an Power Connections 18 1 19 On Board Switches 18 1 20 Supported Operating Systems 18 1 21 BIOS Features 18 1 22 ACPI 19 1 23 Debug Ports 19 1 24 SMBus 19 1 25 DDR3 VREF Control Circuit 20 2 0 CRB Setup 21 2 1 CRB Configuration Setting Notes 21 2 2 Memory Module Plug in 22 2 3 Peripheral Setup 22 2 3 1 Connect SATA Cables 22 2 3 2 Expansion Connectors 22 2 3 3 Rear Panel Connectors 23 2 3 4 SPI Bo...

Page 4: ...odes 53 B 1 Port 0x80 Progress Codes 53 B 2 Port 0x80 Error Codes 55 B 3 Port 0x80 Error Debug 57 Appendix C Board Reference Diagrams 58 Figures 1 Reference Board Overview 6 2 CRB 2 DIMM CH DDR3 Topology 11 3 DIMM Population Within a Channel for Two Slots per Channel 12 4 Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit PCIe Headers 16 5 SMBus Block Diagram 20 6...

Page 5: ...nications Chipset 8910 Development Kit Default Header Configuration 16 12 Rear Panel I O Connectors 16 13 On Board Power Connectors 17 14 Supported BIOS Features 18 15 Effects of Pressing the Power Button 19 16 Serial Console Redirection Default Settings 34 17 Processor Straps Jumper Settings 37 18 PCH Straps Jumper Resistor Settings 37 19 Miscellaneous Jumper Resistor Settings 38 20 Reserved Head...

Page 6: ... Core Processor For Communications Infrastructure Unless otherwise stated references to the chipset Platform Controller Hub or PCH refer to the Intel Communications Chipset 89xx Series The CRB schematics are the primary source for details about the CRB This user guide is a supplement to the schematics Component reference designators in this user s guide are based on the CRB schematics and are defi...

Page 7: ...oard is set up plug the power cable into the back of the power supply leaving the switch in the OFF position then plug the cord into the power source and switch on the power supply Caution Items marked as Reserved in this users guide and in the CRB schematics are not supported Changing settings related to these items could lead to unknown behavior on the CRB 1 2 Kit Contents Feature Description CR...

Page 8: ...echnologies densities PCI Express Total of six slots One x16 slot connected to processor Intel Communications Chipset 89xx Series Endpoint One x8 slot on processor 4 active lanes Four x8 slots from PCH 2 5 GT s Max 1 active lane in each Note PCI Express Base Specification Rev 1 0a PCI Express hot plug Not supported Chipset BGA soldered down Intel Communications Chipset 89xx Series Serial ATA Two S...

Page 9: ...cification Update 328000 Intel Xeon and Intel Core Processors For Communications Infrastructure Thermal Mechanical Design Guide 327397 Intel Communications Chipset 89xx Series Thermal Mechanical Design Guide 328012 JEDEC Memory Specification http www jedec org PCI Express Base Specification Rev 2 0 http www pcisig com specifications PCI Express Base Specification Revision 1 1 http www pcisig com s...

Page 10: ...e http www formfactors org DeveloperResources asp SSI Specification http ssiforum org specifications aspx ATX Specification Rev 2 02 http www formfactors org formfactor asp Socket B Design Guidelines Contact your Intel representative for the latest version of this item 1 5 Processors and Chipset The CRB is designed to support the following processor and chipset Use only the processor and chipset i...

Page 11: ...but only timings that support the slowest DIMM will be applied to all As a consequence faster DIMMs will be operated at timings supported by the slowest DIMM populated The same interface frequency DDR3 1066 or DDR3 1333 will be applied to all DIMMs on all channels on the platform When single and dual rank DIMMs are populated for 2DPC always populate the higher number rank DIMM first starting from ...

Page 12: ...66 2N Single rank Single rank 4 DDR3 1333 1066 2N Single rank Dual rank 5 DDR3 1333 1066 2N Dual rank Dual rank 1 7 Thermal and Mechanical Components Table 3 Thermal and Mechanical Components Name Description Standard Processor Thermal Solution Mounting The CRB supports full power processor thermal solution mounting provisions as delineated in the processor s Thermal Mechanical Design Guidelines P...

Page 13: ...y The battery has an estimated life of three years when it is not plugged into a wall socket When the platform is plugged in the standby current from the power supply extends the life of the battery The clock is accurate to 13 minutes year at 25 ºC with 3 3 VSTBY applied If the battery and AC power fail then at boot up the system will prompt you to either load optimized defaults or enter the BIOS ...

Page 14: ...an Header Four wire CPU fan header J3J1 PCH Fan Header Three wire PCH fan header J5B3 AUX Fan Header Three wire header with no fan speed control J1H2 LPC Header 20 pin card header for the TPM LPC bus J1J1 LCD Data 16 pin header not populated for LCD port 80 output J2J2 PCH In Circuit SPI Programming Header 10 pin header for use with DediProg SF100 in circuit program tool Used to update PCH SPI dev...

Page 15: ...h 3 x8 The PCH EndPoint can operate as a x4 x8 or x16 depending on the SKU and population of the headers below Table 8 Intel Xeon Processor E3 1125C PCIe Port0 Configuration J6F6 CFG 6 Bit J6E4 CFG 5 Bit Intel Xeon Processor E3 1125C Port Bifurication 1 1 x16 1 0 x8 x8 0 1 Reserved 0 0 x8 x4 x4 The Intel Communications Chipset 89xx Series EndPoint also supports lane reversal Lane Reversal and Pola...

Page 16: ...6E2 J3F2 J6E5 J6E6 Description 1 Closed Closed Open Closed Closed X Bifur X4 0 0 Lane Reverse 2 Closed Closed Open Closed Closed X Bifur X4 0 0 Lane Reverse 3 Closed Open Open Closed Closed X Bifur X8 X8 1 0 Lane Reverse 4 Open Open Open Closed Closed X Bifur X16 1 1 Lane Reverse 1 13 Rear Panel I O Connectors Table 12 Rear Panel I O Connectors Ref Des Location Description J8A1 USB Ports 0 3 Conne...

Page 17: ...tor Provides 12 V 12V1 voltages from the external power supply that feed the DIMMs 1 15 Watch Dog Timer WDT The PCH has a safeguard watchdog timer to help prevent processor from thermal overload During the power up sequence the PCH asserts CPUPWRGD If the processor reset handshake is not completed within 10 ms of assertion the PCH will power cycle the system to re attempt the boot It is critical t...

Page 18: ...he PCI Local Bus Specification Rev 2 3 Serial ATA boot The BIOS supports booting from a Serial ATA hard drive CD ROM boot The BIOS supports booting from a Serial ATA CD ROM USB boot The BIOS supports booting from a USB boot device Floppy boot The BIOS supports booting from a floppy drive PCI Express The BIOS initializes and supports PCI Express cards that are plugged into the CRB USB The BIOS supp...

Page 19: ...he system as a whole into a low power state Table 15 Effects of Pressing the Power Button If the system is in this state and the power switch is pressed for the system enters this state Off ACPI G2 G5 soft off Less than four seconds Power on ACPI G0 working state On ACPI G0 working state Less than four seconds Soft off Standby ACPI G1 sleeping state On ACPI G0 working state More than four seconds ...

Page 20: ...the DIMM_VREF_SMB segment of the CRB SMBus The CRB schematics show the digital potentiometers connected in parallel with 12 1 KΩ 12 1 KΩ 1 resistor voltage dividers This must be considered if calculating the resulting VREF voltage for particular settings of the potentiometer Crystal Forest Introduction Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide ...

Page 21: ...ngs may be visible via the CRB schematics These stuffing resistor settings should not be altered unless directed to do so by Intel changes require a board rework The processor straps start being latched when PLTRST CPUPWRGD are asserted by the PCH The latch in the processor closes approximately 250 ns after the de asserting edge of PLTRST The PCH Functional Straps are used for static configuration...

Page 22: ...as the boot drive Port 4 in the Intel Communications Chipset 89xx Series documentation 2 3 2 Expansion Connectors If necessary connect PCI Express add in cards possibly including the video card in the appropriate Slot 1 through Slot 6 PCI Express slots Slot 1 is a x4 link with a x8 connector Some systems may not support Slot 1 or may have issues training with Slot 1 If you encounter issues with Sl...

Page 23: ...er is applied to the CRB the switches used U2J2 and U2J3 will automatically connect the PCH SPI signals to the SPI flash device For the switch to function correctly in Normal Operation Mode jumper J3J3 and J3J4 and the SPI program header J2J2 for Dediprog SF100 must be empty Programming Mode See Dediprog SPI Flash Memory Programming on page 28 Figure 7 SPI In Circuit Programming Intel 8920 System ...

Page 24: ... pick to gently push up from under the lip of Door 1 This is what it looks like with door 1 opened Note SPI flash should be preinstalled 2 Follow the same steps to open door 2 Crystal Forest CRB Setup Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 24 Order No 328009 001US ...

Page 25: ... slots It is not necessary to apply pressure 5 Align the pin 1 indicator on the IC with the pin 1 dot on the board silkscreen CRB Setup Crystal Forest Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No 328009 001US 25 ...

Page 26: ...6 Gently close door 2 and then door 1 Crystal Forest CRB Setup Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 26 Order No 328009 001US ...

Page 27: ...al 1 Follow the steps from SPI Flash Memory Installation on page 23 to open the doors 2 Use tweezers to gently remove the device from the socket 3 Gently close the socket doors to avoid damage CRB Setup Crystal Forest Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No 328009 001US 27 ...

Page 28: ...ithout power on the board it is best to do it with the board powered down 1 Disconnect the Intel Communications Chipset 89xx Series SPI interface to SPI flash by removing the shunt from SPI_PROG jumper J2J1 to program either SPI0 or SPI1 2 Connect Dediprog to Dediprog connector header J2J2 ensuring orientation is correct Use the 10 pin header which has a rainbow of colors Pin 1 of the header squar...

Page 29: ...ter the blank check has been completed without any problem click File to locate and open the file If the suffix is ROM select Data Format ROM if the suffix is BIN select Data Format Raw Binary Click OK You need to program chip 1 and chip 2 Repeat steps 5 through 7 for Chip 1 and 2 using the following files Application Memory Chip 1 Rom00_4M_ST bin Application Memory Chip 2 Rom01_4M bin Note See th...

Page 30: ...set setting because the program saved the last used setting Fill in the Starting Address and Length file size If no offset required select the option for Program a whole file Figure 9 Offset Setting 10 Program Verify Click Prog after save the Offset and File size Finally click Verify to verify the SPI Make sure the checksum matches Figure 10 Offset Verification 11 Done Disconnect the Dediprog cabl...

Page 31: ...lots 2 Insert the 8 pin power plug into the motherboard s J5K2 SSI 8 pin power connector making sure that the plug clip lines up with the clip lock and the connector pins fit easily into their appropriate slots 3 Insert the 4 pin power plug into the motherboard s J9D1 SSI 4 pin power connector making sure that the plug clip lines up with the clip lock and the connector pins fit easily into their a...

Page 32: ...s a Desktop Management Interface DMI compliant method for managing computers in a managed network The main component of SMBIOS is the Management Information Format MIF database which contains information about the computing system and its components Using SMBIOS a system administrator can obtain the system types capabilities operational status and installation dates for system components The MIF d...

Page 33: ...hard drive to be the second 3 5 1 CD ROM Boot Booting from CD ROM is supported in compliance to the El Torito bootable CD ROM format specification Under the Boot menu in the BIOS Setup program ATAPI CD ROM is listed as a boot device Boot devices are defined in priority order Accordingly if there is not a bootable CD in the CD ROM drive the system attempts to boot from the next defined drive 3 5 2 ...

Page 34: ...e boot firmware console redirection is text only Graphical data such as logos are not redirected Table 2 shows the default settings of the serial console redirection Table 16 Serial Console Redirection Default Settings Parameter Default Port Number COM 1 Baud Rate 115200 Data Bits 8 Parity None Stop Bits 1 Flow Control None 3 6 BIOS Security Features The BIOS includes security features that restri...

Page 35: ... look for a descriptor signature on the SPI flash device on Chip Select 0 starting at address 0x10 for the PCH B0 Silicon The descriptor fetch is triggered by either the assertion of MEPWROK or de assertion of LAN_RST whichever occurs first If the signature is present and valid the PCH will boot in Descriptor Mode which is a requirement of the CRB It will load up the descriptor into corresponding ...

Page 36: ...n indication of battery failure is when you must restore your BIOS settings and system time after unplugging the system and plugging it in again With a failed battery this occurs every time power is removed from the power supply A 2 Clearing CMOS Memory 1 Caution Do not move jumpers when the power is on Always turn off the power and unplug the power cord before changing a jumper setting Otherwise ...

Page 37: ...Location Color Default Setting Description INTRUDER Protection INTRUDER_ N J1J2 Black Open Open Normal Closed Disable Power No Reboot NRBOOTS J1H1 Blue Open Open Normal Closed No Reboot Boot Device Select BBS0 J1H3 J1H4 Blue Headers Unpopulated J1H3 J1H4 Operation Open Open SPI default Open Closed Reserved Closed Open Reserved Closed Closed Reserved CMOS Reset J1J5 Blue Shunt 1 2 1 2 Normal 2 3 Re...

Page 38: ...n PCH EP JTAG GPIO25 DDR3 Voltage Select J9C2 Black Open Open VDD1P5_DDR is 1 5V default Closed VDD1P5_DDR is 1 35V PCH WDT Enable J4A1 Black Open When closed this header enables the board to reset the board when the WDT times out CPU Fan Override CPU_FAN_CTRL J7D1 Black Open Open Manual Control Full Speed Closed PWM Control PCH Fan Override PWM2_PCHFAN J3J2 Black Shunt 1 2 Open PWM Control Closed...

Page 39: ...F STBY Only BRD ID EEPROM Write Protect FRUID_WR J1A4 Black Shunt 1 2 Open Write Enable Closed Write protected GbE EEPROM Write Protect J1E1 Black Shunt 1 2 Shunt 1 2 Write Protected Open Allow writes CPU System Agent Voltage Selection VTT_SA_CPU0 J6K1 Black Shunt 2 3 Shunt 1 2 VID0 forced high VOUT 0 5 1 RFS ROFS Shunt 2 3 VID0 forced low VOUT 0 55 1 RFS ROFS CPU System Agent Vsref Selection J6K2...

Page 40: ...aders Table 21 SMBus Headers Jumper Name Ref Des Location Default Setting Description EP_SMBus Header J3D1 Open Header for the PCH Endpoint Header GBE_SMBus Header J4J1 Open GbE SMBus Header PCH_SMLink1 Header J4J2 Open PCH SMLink Header SMBus PCH PCIe Slot Header J5B2 Open Header on PCIe SMBus SMBus PCH DDR VREF Header J7D2 Open Header on DDR VREF SMBus SMBus PCH LPC TPM Header J1B2 Open Header o...

Page 41: ...urement VCC1P0_PCH J1A5 Open 1 0V PCH voltage measurement VCC1P0_STBY J1A2 Open 1 0V standby voltage measurement VCC1P0_AUX J1A6 Open 1 0V aux voltage measurement VCC1P8_AUX J3A1 Open 1 8V aux voltage measurement VCC1P8_STBY J1A3 Open 1 8V standby voltage measurement VCC1P8_PCH J1H5 Open 1 8V PCH voltage measurement VCCDMI_PCH J3H1 Open 1 05V DMI voltage measurement VCC1P05_AUX J3E1 Open 1 05V aux...

Page 42: ...K DS1F1 Green PCH_PWROK signal is active Sleep S3 DS1F3 Yellow PCH_S3_N signal is active Sleep S4 DS1F2 Yellow PCH_S4_N signal is active Sleep S5 DS1F5 Yellow PCH_S5_N signal is active Resume Reset DS1F4 Red RSMRST signal is active Platform Reset DS6A1 Red PLTRST_N signal is active SATA Hard Drive Active DS1B1 Green SATA_HD_LED_N signal is active LAN Link Status GBE_LED 3 0 DS2E1 DS2E2 DS2E3 DS2E4...

Page 43: ...5 1 GND 12 V 12V1 6 2 GND 12 V 12V1 7 3 GND 12 V 12V1 8 4 GND Table 26 4 pin DDR Power Connector Pins Top View Signal Name Pin Pin Signal Name 12 V 12V1 3 1 GND 12 V 12V1 4 2 GND A 10 Front Panel Connector Table 27 9 pin Front Panel Connector Pins Top View Description Signal Name Pi n Pi n Signal Name Description PU resistor 5V for hard drive LED FP_VCC_HDLED 1 2 FP_LED_GRN_N ATX power on indicato...

Page 44: ...e I O xAPIC is supported by Microsoft OS s Table 28 I O xAPIC Interrupt Mapping 1 IRQ 2 Via SERIRQ Via PCI Message System Resource 0 No No Cascade from 8259 1 1 Yes Yes 2 No No 8254 Counter 0 HPET 0 legacy mode 3 Yes Yes 4 Yes Yes 5 Yes Yes 6 Yes Yes 7 Yes Yes 8 No No Real time clock HPET 1 legacy mode 9 Yes Yes Option for SCI TCO 10 Yes Yes Option for SCI TCO 11 Yes Yes HPET 2 option for SCI TCO ...

Page 45: ...ed to support the C3 state It indicates that a bus master device is busy When this signal is asserted the BM_STS bit will be set If this signal goes active in a C3 state it is treated as a break event This signal is internally synchronized using the PCICLK and a two stage synchronizer It does not need to meet any particular setup or hold time This signal can also be used as GPIO Port 0 GPIO1 I O G...

Page 46: ...ndication this signal should be drive to 0 to indicate that the switch is closed and to 1 to indicate that the switch is open If interlock switches are not required this pin can be configured as GPIO port 16 GPIO17 I O GPI 1 I CORE Platform Dependent General Purpose I O Port 17 Not Multiplexed This signal strapping sets the DMI termination voltage GPIO18 I O Native 1 I CORE General Purpose I O Por...

Page 47: ... Multiplexed Flash Descriptor Security Overwrite This signal is used to set the security override strap on the PCH If sampled low the Flash Descriptor Security will be overridden If high the security measures defined in the Flash Descriptor will be in effect This strap should only be enabled pulled low in manufacturing environments using an external pull down resistor GPIO33 0 Enable Pull Down Req...

Page 48: ...ls set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred OC 3 0 may optionally be used as GPIO Ports 42 41 40 59 Note 1 OC pins are 3 3V and NOT 5V tolerant 2 OC pins must be shared between ports 3 OC 3 0 can only be used for EHCI controller 1 OC2 GPIO41 2 I O OC2 1 I SUS Overcurrent Indicators These signals set corresponding bits in the USB controlle...

Page 49: ...ut pin which can be configured as an interlock switch corresponding to SATA Port 5 When used as an interlock switch status indication this signal should be drive to 0 to indicate that the switch is closed and to 1 to indicate that the switch is open Temperature Alert Used as an alert active low to indicate to the external controller such as EC or SIO that temperatures are out of range for the PCH ...

Page 50: ...readable via the Top Swap bit Chipset Config Registers Offset 3414h bit 0 Software will not be able to clear the Top Swap bit until the system is rebooted without GPIO55 being pulled down GPIO56 I O Native 1 I SUS General Purpose I O Port 56 Not Multiplexed 3 GPIO57 I O GPI 1 I SUS General Purpose I O Port 57 Not Multiplexed SML1CLK GPIO58 I O SML1CL K 1 I SUS When SMBUS External pull up required ...

Page 51: ...O Native 1 I SUS General Purpose I O Port 72 Not Multiplexed 3 GPIO73 I O Native 1 I SUS General Purpose I O Port 73 Not Multiplexed 3 SML1ALER T GPIO74 2 I O SML1AL ERT 1 I SUS When SMBUS External pull up required System Management Link Alert 1 This signal can be connected to an external BMC External pull up resistor to VCCSUS3P3 is required Resistor value should be calculated based on the bus lo...

Page 52: ...may change to reflect the Soft Strap configuration even though GPIO Lockdown Enable GLE bit is set For signals that have Native defaults these signals must be configured by using SPI Soft Strap 4 The functionality that is multiplexed with the GPIO may not be used in desktop configuration 5 In a ME disabled system GPIO31 may be used as ACPRESENT from the EC Crystal Forest Technical Reference Intel ...

Page 53: ... during Sec Phase 0x06 Early SB initialization during Sec Phase 0x07 Early NB initialization during Sec Phase 0x08 End Of Sec Phase 0x09 Microcode Not Found 0x0E Microcode Not Loaded 0x0F PEI Phase PEI Core Initialization 0x10 CPU PEIM Initialization 0x11 NB PEIM Initialization 0x15 SB PEIM Initialization 0x19 Memory Detection PEIM SPD READ 0x1D Memory Detection PEIM Memory Presence Detect 0x1E Me...

Page 54: ...ion 0x72 DXE ACPI Initialization 0x78 DXE CSM Initialization 0x79 DXE BDS Started 0x90 DXE BDS connect drivers 0x91 DXE PCI Bus begin 0x92 DXE PCI Bus HPC Initialization 0x93 DXE PCI Bus enumeration 0x94 DXE PCI Bus resource requested 0x95 DXE PCI Bus assign resource 0x96 DXE CON_OUT connect 0x97 DXE CON_IN connect 0x98 DXE SIO Initialization 0x99 DXE USB start 0x9A DXE USB reset 0x9B DXE USB dete...

Page 55: ...set 0xB7 CSM16 0x00 S3 Resume PEIM S3 started 0xE0 S3 Resume PEIM S3 boot script 0xE1 S3 Resume PEIM S3 Video Repost 0xE2 S3 Resume PEIM S3 OS wake 0xE3 PEIM which detected forced Recovery condition 0xF0 PEIM which detected User Recovery condition 0xF1 Recovery PEIM Recovery started 0xF2 Recovery PEIM Capsule found 0xF3 Recovery PEIM Capsule loaded 0xF4 B 2 Port 0x80 Error Codes Table 31 Port 0x80...

Page 56: ... not available 0xD3 Out of resources for PCI device 0xD4 Insufficient space to dispatch legacy option ROM 0xD5 No Console Output device detected 0xD6 No Console Input device detected 0xD7 Invalid Password 0xD8 Error loading the boot option 0xD9 Boot Option failure 0xDA Flash updated failure 0xDB DXE reset not available 0xDC S3 resume memory failure 0xE8 S3 resume PPI not found 0xE9 S3 Boot Script ...

Page 57: ...memory may have been corrupted Run Setup to reset values Memory Size Decreased Memory size has decreased since the last boot If no memory was removed then memory may be bad No Boot Device Available System did not find a device to boot Error Messages and LED Codes Crystal Forest Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No 328...

Page 58: ...ard Reference Diagrams Figure 11 Top View Crystal Forest Board Reference Diagrams Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 58 Order No 328009 001US ...

Page 59: ...gure 12 DDR3 Memory Components Board Reference Diagrams Crystal Forest Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No 328009 001US 59 ...

Page 60: ...lots Figure 14 PECI Thermal Diode Components Crystal Forest Board Reference Diagrams Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 60 Order No 328009 001US ...

Page 61: ... 15 LEDs and Power Button Switches Board Reference Diagrams Crystal Forest Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No 328009 001US 61 ...

Page 62: ...igure 16 Power Supply Headers Crystal Forest Board Reference Diagrams Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 62 Order No 328009 001US ...

Page 63: ...Figure 17 SMBus Headers Board Reference Diagrams Crystal Forest Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No 328009 001US 63 ...

Page 64: ...Configuration Jumper Locations 1 of 2 Crystal Forest Board Reference Diagrams Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 64 Order No 328009 001US ...

Page 65: ...Configuration Jumper Locations 2 of 2 Board Reference Diagrams Crystal Forest Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No 328009 001US 65 ...

Page 66: ... Communications Chipset 89xx Series Straps Crystal Forest Board Reference Diagrams Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit User Guide October 2012 66 Order No 328009 001US ...

Page 67: ...essor For Communications Infrastructure Straps Figure 22 Front Panel Board Reference Diagrams Crystal Forest Intel Xeon Processor E3 1125C with Intel Communications Chipset 8910 Development Kit October 2012 User Guide Order No 328009 001US 67 ...

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