Figure 2.
CRB 2 DIMM/CH DDR3 Topology
Processor
D
I
M
M
B1
D
I
M
M
B0
D
I
M
M
A1
D
I
M
M
A0
Channel A
Channel B
1.6.1
Supported Memory
The CRB supports DDR3-1066 and DDR3-1333 memory technologies.
The processor has a two-channel memory interface. Each channel consists of 64 data
and 8 ECC bits. The CRB supports unbuffered ECC/non-ECC DDDR3 DIMMs.
1.6.1.1
Population Requirements
•
All DIMMs must be DDR3 Unbuffered DIMMs.
•
Unbuffered DIMMs can be ECC or non-ECC.
•
Mixing of ECC and non-ECC DIMMs is not allowed.
•
A maximum of 4 logical ranks per channel is allowed.
•
DIMMs with different timing parameters can be installed on different slots within
the same channel, but only timings that support the slowest DIMM will be applied
to all. As a consequence, faster DIMMs will be operated at timings supported by
the slowest DIMM populated. The same interface frequency (DDR3-1066 or
DDR3-1333) will be applied to all DIMMs on all channels on the platform.
•
When single and dual rank DIMMs are populated for 2DPC, always populate the
higher number rank DIMM first (starting from the farthest slot), for example, first
dual rank and last single rank.
1.6.1.2
DIMM Population for Two Slots per Channel
For two slot per channel configurations, the CRB requires DIMMs within a channel to
be populated starting with the DIMMs farthest from the processor in a “fill-farthest”
approach.
Introduction—Crystal Forest
Intel
®
Xeon
®
Processor E3-1125C with Intel
®
Communications Chipset 8910 Development Kit
October 2012
User Guide
Order No.: 328009-001US
11
