Description 11
Intel
®
E7501 Chipset
The Server Board SE7501CW2 includes the Intel
E7501 chipset (MCH, ICH3-S, P64H2), which
provides an integrated I/O bridge and memory controller, and a flexible I/O subsystem core (PCI).
MCH
The E7501 MCH North Bridge in the E7501 chipset integrates three main functions:
•
An integrated high-performance main memory subsystem
•
An HI 2.0 bus interface that provides a high-performance data flow path between the host bus
and the I/O subsystem
•
A HI 1.5 bus that provides an interface to the ICH3-S (South Bridge)
Other features provided by the MCH include the following:
•
Full support of ECC on the memory bus
•
Full support of Intel® x4 Single Device Data Correction on the memory interface with x4
DIMMs
•
Twelve deep in-order queue
•
Full support of registered DDR200 or DDR266 ECC DIMMs
2
•
Support for up to 8 GB of DDR memory
•
Memory scrubbing
ICH3-S I/O Controller Hub
The primary role of the ICH3-S is to provide the gateway to all PC-compatible I/O devices and
features. The Server Board SE7501CW2 uses the following ICH3-S features:
•
32-bit/33 MHz PCI bus interface
•
Low Pin Count (LPC) bus interface
•
IDE interface, with Ultra DMA 100 capability
•
Universal Serial Bus (USB) interface
•
PC-compatible timer/counter and DMA controllers
•
APIC and 8259 interrupt controller
•
Power management
•
System real-time clock (RTC)
•
General purpose I/O
2
DDR200 compliant ECC DIMMs can be used only if 400 MHz processors are installed.