Signal Definitions
80
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
BINIT#
I/O
BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents
and if used, must connect the appropriate pins of all such agents. If the BINIT# driver
is enabled during power on configuration, BINIT# is asserted to signal any bus
condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration (see
Section 7.1
) and
BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and
bus request arbitration state machines. The bus agents do not reset their I/O Queue
(IOQ) and transaction tracking state machines upon observation of BINIT# assertion.
Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the
FSB and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a priority agent may
handle an assertion of BINIT# as appropriate to the error handling architecture of the
system.
3
BNR#
I/O
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wired-OR signal which must connect the appropriate pins of all processor FSB agents.
In order to avoid wired-OR glitches associated with simultaneous edge transitions
driven by multiple drivers, BNR# is activated on specific clock edges and sampled on
specific clock edges.
3
BPM5#
BPM4#
BPM3#
BPM[2:1]#
BPM0#
I/O
O
I/O
O
I/O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[5:0]#
should connect the appropriate pins of all FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a
processor output used by debug tools to determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used
by debug tools to request debug operation of the processors.
BPM[5:4]# must be bussed to all bus agents. Please refer to the appropriate platform
design guidelines for more detailed information.
2
BPMb3#
BPMb[2:1]#
BPMb0#
I/O
O
I/O
BPMb[3:0]# (Breakpoint Monitor) are a second set of breakpoint and performance
monitor signals. They are additional outputs from the processor which indicate the
status of breakpoints and programmable counters used for monitoring processor
performance. BPMb[3:0]# should connect the appropriate pins of all FSB agents.
2
BPRI#
I
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB.
It must connect the appropriate pins of all processor FSB agents. Observing BPRI#
active (as asserted by the priority agent) causes all other agents to stop issuing new
requests, unless such requests are part of an ongoing locked operation. The priority
agent keeps BPRI# asserted until all of its requests are completed, then releases the
bus by deasserting BPRI#.
3
BR[1:0]#
I/O
The BR[1:0]# signals are sampled on the active-to-inactive transition of RESET#. The
signal which the agent samples asserted determines its agent ID. BR0# drives the
BREQ0# signal in the system and is used by the processor to request the bus.
These signals do not have on-die termination and must be terminated.
3
BSEL[2:0]
O
The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor
input clock frequency.
Table 2-2
defines the possible combinations of the signals and
the frequency associated with each combination. The required frequency is
determined by the processors, chipset, and clock synthesizer. All FSB agents must
operate at the same frequency. For more information about these signals, including
termination recommendations, refer to the appropriate platform design guideline.
COMP[3:0]
I
COMP[3:0] must be terminated to VSS on the baseboard using precision resistors.
These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate
platform design guidelines for implementation details.
Table 5-1.
Signal Definitions (Sheet 2 of 7)
Name
Type
Description
Notes
Summary of Contents for Quad-Core Xeon
Page 1: ...Order Number 315569 003 Quad Core Intel Xeon Processor 5300 Series Datasheet September 2007...
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Page 54: ...Mechanical Specifications 56 Quad Core Intel Xeon Processor 5300 Series Datasheet...
Page 84: ...Signal Definitions 86 Quad Core Intel Xeon Processor 5300 Series Datasheet...
