Thermal Management
60
Datasheet
•
It can accurately track the die temperature and ensure that the Adaptive Thermal
Monitor is not excessively activated.
Temperature values from the DTS can be retrieved through
•
A software interface via processor Model Specific Register (MSR).
•
A processor hardware interface as described in
Note:
When temperature is retrieved by processor MSR, it is the instantaneous temperature
of the given core. When temperature is retrieved via PECI, it is the average
temperature of each execution core’s DTS over a programmable window (default
window of 256 ms.) Intel recommends using the PECI output reading for fan speed or
other platform thermal control.
Code execution is halted in C1-C6. Therefore temperature cannot be read via the
processor MSR without bringing a core back into C0. However, temperature can still be
monitored through PECI in lower C-states.
Unlike traditional thermal devices, the DTS outputs a temperature relative to the
maximum supported operating temperature of the processor (T
j,max
). It is the
responsibility of software to convert the relative temperature to an absolute
temperature. The absolute reference temperature is readable in an MSR. The
temperature returned by the DTS is an implied negative integer indicating the relative
offset from T
j,max
. The DTS does not report temperatures greater than T
j,max
.
The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor
trigger point. When a DTS indicates that the maximum processor core temperature has
been reached (a reading of 0x0 on any core), the TCC will activate and indicate a
Adaptive Thermal Monitor event.
Changes to the temperature can be detected via two programmable thresholds located
in the processor thermal MSRs. These thresholds have the capability of generating
interrupts via the core's local APIC. Refer to the
Intel® 64 and IA-32 Architectures
Software Developer's Manuals
for specific register and programming details.
5.2.1.3
PROCHOT# Signal
PROCHOT# (processor hot) is asserted when the processor core temperature has
reached its maximum operating temperature (T
j,max
). This will activate the TCC and
signal a thermal event which is then resolved by the Adaptive Thermal Monitor. See
(above) for a timing diagram of the PROCHOT# signal assertion relative to
the Adaptive Thermal Response.
Only a single PROCHOT# pin exists at a package level
of the processor. When any core arrives at the TCC activation point, the PROCHOT#
signal will be driven by the processor core. PROCHOT# assertion policies are
independent of Adaptive Thermal Monitor enabling.
Note:
Bus snooping and interrupt latching are active while the TCC is active.
