Datasheet
43
Power Management
4.2.4
Core C-states
The following are general rules for all core C-states, unless specified otherwise:
•
A core C-State is determined by the lowest numerical thread state (e.g., Thread 0
requests C1E while Thread 1 requests C3, resulting in a core C1E state). See
.
•
A core transitions to C0 state when:
— An interrupt occurs
— There is an access to the monitored address if the state was entered via an
MWAIT instruction
•
For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes
only that thread. However, since both threads are no longer at the same core
C-state, the core resolves to C0.
•
For core C6, an interrupt coming into either thread wakes both threads into C0
state.
•
Any interrupt coming into the processor package may wake any core.
4.2.4.1
Core C0 State
The normal operating state of a core where code is being executed.
4.2.4.2
Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the
Intel
®
64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see
.
4.2.4.3
Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
