Datasheet
59
Thermal Management
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On a downward transition, the frequency transition precedes the voltage transition.
When transitioning to a target core operating voltage, a new VID code to the voltage
regulator is issued. The voltage regulator must support dynamic VID steps to support
this method.
During the voltage change:
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It will be necessary to transition through multiple VID steps to reach the target
operating voltage.
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Each step is 12.5 mV for Intel MVP-6.5 compliant VRs.
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The processor continues to execute instructions. However, the processor will halt
instruction execution for frequency transitions.
If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition
(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are
two possible outcomes:
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If the P-state target frequency is higher than the processor core optimized target
frequency, the p-state transition will be deferred until the thermal event has been
completed.
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If the P-state target frequency is lower than the processor core optimized target
frequency, the processor will transition to the P-state operating point.
5.2.1.1.2
Clock Modulation
If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor
event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is
done by alternately turning the clocks off and on at a duty cycle (ratio between clock
“on” time and total time) specific to the processor. The duty cycle is factory configured
to 37.5% on and 62.5% off and cannot be modified. The period of the duty cycle is
configured to 32 microseconds when the TCC is active. Cycle times are independent of
processor frequency. A small amount of hysteresis has been included to prevent
excessive clock modulation when the processor temperature is near its maximum
operating temperature. Once the temperature has dropped below the maximum
operating temperature, and the hysteresis timer has expired, the TCC goes inactive and
clock modulation ceases. Clock modulation is automatically engaged as part of the TCC
activation when the frequency/VID targets are at their minimum settings. Processor
performance will be decreased by the same amount as the duty cycle when clock
modulation is active. Snooping and interrupt processing are performed in the normal
manner while the TCC is active.
5.2.1.2
Digital Thermal Sensor
Each processor execution core has an on-die Digital Thermal Sensor (DTS) which
detects the core’s instantaneous temperature. The DTS is the preferred method of
monitoring processor die temperature because
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It is located near the hottest portions of the die.
