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Datasheet

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IA-32 Intel

Architecture Software Developer's Manual

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Volume 1: Basic Architecture

Volume 2A: Instruction Set Reference

Volume 2B: Instruction Set Reference

Volume 3: System Programming Guide

Table 1-1. References (Sheet 2 of 2)

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Summary of Contents for Pentium M 715

Page 1: ...Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache Datasheet January 2006 Document Number 302189 008...

Page 2: ...rved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Pentium M proc...

Page 3: ...Electrical Specifications 17 3 1 Power and Ground Pins 17 3 1 1 FSB Clock BCLK 1 0 and Processor Clocking 17 3 2 Voltage Identification 17 3 3 Catastrophic Thermal Protection 18 3 4 Signal Termination...

Page 4: ...of Active State VCC Static and Ripple Tolerances HFM VID D 37 3 8 Illustration of Deep Sleep State VCC Static and Ripple Tolerances LFM VID D 38 3 9 Illustration of Active State VCC Static and Ripple...

Page 5: ...Tolerances for the Intel Pentium M Processor Active State VID D 37 3 15Voltage Tolerances for the Intel Pentium M Processor Deep Sleep State VID D 38 3 16Voltage Tolerances for the Intel Pentium M Pr...

Page 6: ...ns updated July 2004 004 Added Intel Pentium M processor 765 specifications October 2004 005 Added Intel Pentium M processor 753 and 758 specifications Added Execute Disable support feature and lead f...

Page 7: ...rchitecture Way set associativity and ECC Error Correcting Code support Data Prefetch Logic Streaming SIMD extensions 2 SSE2 400 MHz source synchronous FSB Advanced power management features including...

Page 8: ...ogy with low power enhancements The processor features Enhanced Intel SpeedStep technology which enables real time dynamic switching between multiple voltage and frequency points This results in optim...

Page 9: ...le 1 1 References Sheet 1 of 2 Document Document Number Location1 Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache Specification Update http www intel com design mobile specupdt 302209 ht...

Page 10: ...cument IA 32 Intel Architecture Software Developer s Manual http www intel com design pentium4 manuals index_new htm Volume 1 Basic Architecture Volume 2A Instruction Set Reference Volume 2B Instructi...

Page 11: ...MI INIT LINT 1 0 NMI INTR or FSB interrupt message RESET will cause the processor to immediately initialize itself A system management interrupt SMI handler will return execution to either Normal stat...

Page 12: ...s a snoop on the FSB see Section 2 1 3 A transition to the Sleep state see Section 2 1 5 will occur with the assertion of the SLP signal While in the Stop Grant State SMI INIT and LINT 1 0 will be lat...

Page 13: ...r is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin See Section 2 1 6 While the processor is in the Sleep state the SLP pin must be deasserted if another...

Page 14: ...cy If the target frequency is higher than the current frequency Vcc is ramped up by placing a new value on the VID pins and the PLL then locks to the new frequency If the target frequency is lower tha...

Page 15: ...The on die termination on the processor FSB buffers is disabled when the signals are driven low resulting in additional power savings The low I O termination voltage is on a dedicated voltage plane in...

Page 16: ...16 Datasheet Low Power Features...

Page 17: ...ck BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the system bus interface speed as well as the core frequency of the processor As in previous generation processors the Pentium M processor...

Page 18: ...0 1 1 692 1 0 0 0 0 1 1 180 0 0 0 0 1 0 1 676 1 0 0 0 1 0 1 164 0 0 0 0 1 1 1 660 1 0 0 0 1 1 1 148 0 0 0 1 0 0 1 644 1 0 0 1 0 0 1 132 0 0 0 1 0 1 1 628 1 0 0 1 0 1 1 116 0 0 0 1 1 0 1 612 1 0 0 1 1...

Page 19: ...hipset MCH and clock generator on Intel 915 Express chipset family based platforms These signals must be left unconnected on platforms designed with the Intel 855 chipset family On these platforms FSB...

Page 20: ...specifications for the CMOS signal groups Table 3 2 FSB Pin Groups Signal Group Type Signals1 AGTL Common Clock Input Synchronous to BCLK 1 0 BPRI DEFER DPWR PREQ RESET RS 2 0 TRDY AGTL Common Clock...

Page 21: ...s are listed in Table 3 24 and Table 3 25 Table 3 4 through Table 3 25 list the DC specifications for the Pentium M processor and are valid only while meeting specifications for junction temperature c...

Page 22: ...1 036 1 036 1 052 600 MHz 0 988 0 988 0 988 0 988 VCCD755 Pentium M Processor 755 Core VCC for Enhanced Intel SpeedStep Technology Operating Points V 1 2 2 0 GHz 1 340 1 324 1 308 1 276 1 8 GHz 1 292...

Page 23: ...l SpeedStep Technology Operating Points V 1 2 1 7 GHz 1 340 1 324 1 308 1 276 1 4 GHz 1 244 1 244 1 228 1 212 1 2 GHz 1 180 1 180 1 164 1 148 1 0 GHz 1 116 1 116 1 116 1 100 800 MHz 1 052 1 052 1 052...

Page 24: ...Intel SpeedStep Technology Operating Points V 1 2 1 6 GHz 1 116 1 5 GHz 1 116 1 4 GHz 1 100 1 3 GHz 1 084 1 2 GHz 1 068 1 1 GHz 1 052 1 0 GHz 1 052 900 GHz 1 036 800 MHz 1 020 600 MHz 0 988 VCCD758 Pe...

Page 25: ...ite side of the processor s socket or BGA ball with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 M minimum impedance The maximum length of ground wire on the probe should be...

Page 26: ...4 0 844 0 844 0 844 600 MHz 0 812 0 812 0 812 0 812 0 812 0 812 VCCD753 Pentium M Processor Ultra Low Voltage 753 Core VCC for Enhanced Intel SpeedStep Technology Operating Points V 2 3 1 2 GHz 0 956...

Page 27: ...ns are assumed to be measured at a via on the motherboard s opposite side of the processor s socket or BGA ball with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 M minimum i...

Page 28: ...9 753 733J 733 723 1 425 1 5 1 575 VCCDPRS LP TR1 Transient Deeper Sleep Voltage 0 695 0 748 0 795 V 2 VCCDPRS LP ST1 Static Deeper Sleep Voltage 0 705 0 748 0 785 V 2 VCCDPRS LP TR2 Transient Deeper...

Page 29: ...758 738 735 725 715 at LFM Vcc 5 9 765 755 745 735 725 715 at HFM Vcc 14 8 778 758 738 at HFM Vcc 6 2 773 753 733J at LFM Vcc 2 2 733 723 at LFM Vcc 2 0 773 753 733J at HFM Vcc 3 2 733 723 at HFM Vcc...

Page 30: ...ms should be designed to this specification 6 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal VCC Not 100 tested 7 Measured...

Page 31: ...1 334 5 5 0 971 0 957 0 986 0 947 0 996 13 0 1 301 1 281 1 321 1 271 1 331 6 0 0 970 0 955 0 985 0 945 0 995 13 9 1 298 1 278 1 318 1 268 1 328 6 4 0 969 0 954 0 984 0 944 0 994 14 8 1 296 1 275 1 31...

Page 32: ...1 324 1 274 1 334 2 7 0 968 0 953 0 983 0 943 0 993 7 6 1 301 1 281 1 321 1 271 1 331 3 1 0 967 0 952 0 982 0 942 0 992 8 5 1 298 1 278 1 318 1 268 1 328 3 5 0 966 0 951 0 981 0 941 0 991 9 5 1 296 1...

Page 33: ...318 5 5 0 971 0 957 0 986 0 947 0 996 13 0 1 285 1 265 1 305 1 255 1 315 6 0 0 970 0 955 0 985 0 945 0 995 13 9 1 282 1 262 1 302 1 252 1 312 6 4 0 969 0 954 0 984 0 944 0 994 14 8 1 280 1 260 1 299 1...

Page 34: ...1 308 1 258 1 318 2 7 0 968 0 953 0 983 0 943 0 993 7 6 1 285 1 266 1 305 1 256 1 315 3 1 0 967 0 952 0 982 0 942 0 992 8 5 1 283 1 263 1 302 1 253 1 312 3 5 0 966 0 951 0 981 0 941 0 991 9 5 1 280 1...

Page 35: ...302 5 5 0 971 0 957 0 986 0 947 0 996 13 0 1 269 1 249 1 289 1 239 1 299 6 0 0 970 0 955 0 985 0 945 0 995 13 9 1 266 1 247 1 286 1 237 1 296 6 4 0 969 0 954 0 984 0 944 0 994 14 8 1 264 1 244 1 283 1...

Page 36: ...1 292 1 243 1 302 2 7 0 968 0 953 0 983 0 943 0 993 7 6 1 270 1 250 1 289 1 240 1 299 3 1 0 967 0 952 0 982 0 942 0 992 8 5 1 267 1 247 1 286 1 237 1 296 3 5 0 966 0 951 0 981 0 941 0 991 9 5 1 264 1...

Page 37: ...1 269 5 5 0 971 0 957 0 986 0 947 0 996 13 0 1 237 1 218 1 256 1 208 1 266 6 0 0 970 0 955 0 985 0 945 0 995 13 9 1 234 1 215 1 253 1 205 1 263 6 4 0 969 0 954 0 984 0 944 0 994 14 8 1 232 1 212 1 25...

Page 38: ...2 1 260 1 212 1 270 2 7 0 968 0 953 0 983 0 943 0 993 7 6 1 238 1 219 1 257 1 209 1 267 3 1 0 967 0 952 0 982 0 942 0 992 8 5 1 235 1 216 1 254 1 206 1 264 3 5 0 966 0 951 0 981 0 941 0 991 9 5 1 232...

Page 39: ...1 340 1 290 1 350 5 5 0 971 0 957 0 986 0 947 0 996 13 0 1 317 1 297 1 337 1 287 1 347 6 0 0 970 0 955 0 985 0 945 0 995 13 9 1 314 1 294 1 335 1 284 1 345 6 4 0 969 0 954 0 984 0 944 0 994 14 8 1 31...

Page 40: ...0 1 340 1 290 1 350 2 7 0 968 0 953 0 983 0 943 0 993 7 6 1 317 1 297 1 337 1 287 1 347 3 1 0 967 0 952 0 982 0 942 0 992 8 5 1 314 1 294 1 335 1 284 1 345 3 5 0 966 0 951 0 981 0 941 0 991 9 5 1 311...

Page 41: ...0 975 0 960 0 990 0 950 1 000 4 9 1 101 1 085 1 118 1 075 1 128 4 7 0 974 0 959 0 989 0 949 0 999 5 3 1 100 1 083 1 117 1 073 1 127 5 1 0 973 0 958 0 987 0 948 0 997 5 8 1 099 1 082 1 115 1 072 1 125...

Page 42: ...811 0 798 0 823 0 788 0 833 0 8 0 938 0 924 0 952 0 914 0 962 0 6 0 810 0 797 0 823 0 787 0 833 1 0 0 937 0 923 0 951 0 913 0 961 0 8 0 809 0 797 0 822 0 787 0 832 1 3 0 936 0 922 0 950 0 912 0 960 1...

Page 43: ...6 0 924 0 910 0 938 0 900 0 948 1 1 0 799 0 754 0 844 0 754 0 845 1 8 0 923 0 909 0 937 0 899 0 947 1 2 0 799 0 754 0 843 0 753 0 844 2 0 0 923 0 909 0 937 0 899 0 947 1 3 0 798 0 754 0 843 0 753 0 84...

Page 44: ...tance only No package parasitics are included 6 VCROSS is defined as the total variation of all crossing voltages as defined in note 2 Figure 3 12 Deep Sleep VCC and ICC Load Line Table 3 22 FSB Diffe...

Page 45: ...included NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The VCCP referred to in these specifications refers to instantaneous VCCP 3 Refer to the...

Page 46: ...CP Please refer to the platform design guides for details 4 For Vin between 0 V and VOH 5 Cpad includes die capacitance only No package parasitics are included Table 3 25 Open Drain Signal Group DC Sp...

Page 47: ...y have capacitors placed in the area surrounding the die Because the die side capacitors are electrically conductive and only slightly shorter than the die height care should be taken to avoid contact...

Page 48: ...A Package Top and Side Views 35 E 35 D PIN A1 CORNER E1 D1 A 1 25 MAX A3 0 32 B 478 places 2 03 0 08 A1 A2 SU BSTR ATE KEEPO U T ZO N E D O N O T C ON TAC T PAC KAG E IN SID E TH IS LIN E 7 K1 8 place...

Page 49: ...ns in millimeters Values shown for reference only Refer to Table 4 1 for details Figure 4 3 Micro FCPGA Package Bottom View 1 2 3 4 6 8 10 12 14 16 18 20 22 24 26 5 7 9 11 13 15 17 19 21 23 25 A B C E...

Page 50: ...top of die to package seating plane 1 88 2 02 mm Overall height top of die to PCB surface including socket Refer to Note 1 4 74 5 16 mm A1 Pin length 1 95 2 11 mm A2 Die height 0 820 mm A3 Pin side c...

Page 51: ...Datasheet 51 Package Mechanical Specifications and Pin Information Figure 4 4 Micro FCBGA Package Top and Bottom Isometric Views TOP VIEW BOTTOM VIEW LABEL DIE PACKAGE KEEPOUT CAPACITOR AREA...

Page 52: ...kage All dimensions in millimeters Values shown for reference only Refer to Table 4 2 for details Figure 4 5 Micro FCBGA Package Top and Side Views 35 E 35 D PIN A1 CORNER E1 D1 A 0 78 b 479 places K2...

Page 53: ...l height as delivered Refer to Note 1 2 60 2 85 mm A2 Die height 0 82 mm b Ball diameter 0 78 mm D Package substrate length 34 9 35 1 mm E Package substrate width 34 9 35 1 mm D1 Die length 12 54 mm E...

Page 54: ...n List Figure 4 7 on the next page shows the top view pinout of the Pentium M Processor The pin list arranged in two different formats is shown in the following pages Figure 4 6 Micro FCBGA Package Bo...

Page 55: ...P D 24 VSS D 28 D 19 VCCA 2 ADS VSS BR0 VCCP VSS VCCP VSS VSS D 27 D 30 VSS REQ 3 VSS REQ 1 A 3 VSS VCCP VSS VCCP VCCQ 0 VSS COMP 0 COMP 1 VSS REQ 0 A 6 VSS VCCP VSS VCCP VSS D 39 D 37 VSS D 38 REQ 4...

Page 56: ...56 Datasheet Package Mechanical Specifications and Pin Information This page is intentionally left blank...

Page 57: ...LK 0 B15 Bus Clock Input BCLK 1 B14 Bus Clock Input BNR L1 Common Clock Input Output BPM 0 C8 Common Clock Output BPM 1 B8 Common Clock Output BPM 2 A9 Common Clock Output BPM 3 C9 Common Clock Input...

Page 58: ...D 61 AF25 Source Synch Input Output D 62 AF22 Source Synch Input Output D 63 AF26 Source Synch Input Output DBR A7 CMOS Output Table 4 3 Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type...

Page 59: ...r Other VCC E21 Power Other VCC F6 Power Other VCC F8 Power Other Table 4 3 Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction VCC F18 Power Other VCC F20 Power Other VCC F22 Pow...

Page 60: ...CP F16 Power Other VCCP K6 Power Other VCCP L5 Power Other Table 4 3 Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction VCCP L21 Power Other VCCP M6 Power Other VCCP M22 Power Ot...

Page 61: ...Power Other VSS F9 Power Other VSS F11 Power Other Table 4 3 Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction VSS F13 Power Other VSS F15 Power Other VSS F17 Power Other VSS F1...

Page 62: ...er Other VSS AA10 Power Other Table 4 3 Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction VSS AA12 Power Other VSS AA14 Power Other VSS AA16 Power Other VSS AA18 Power Other VSS...

Page 63: ...in Output Table 4 3 Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction A13 TCK CMOS Input A14 VSS Power Other A15 ITP_CLK 1 CMOS input A16 ITP_CLK 0 CMOS input A17 VSS Power Othe...

Page 64: ...AC9 VCC Power Other AC10 VSS Power Other Table 4 4 Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction AC11 VCC Power Other AC12 VSS Power Other AC13 VCC Power Other AC14 VSS P...

Page 65: ...Output AF5 VSS Power Other AF6 VSSSENSE Power Other Output AF7 RSVD Reserved AF8 VCC Power Other Table 4 4 Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction AF9 VSS Power Othe...

Page 66: ...LINT0 CMOS Input D2 VSS Power Other D3 FERR Open Drain Output D4 LINT1 CMOS Input D5 VSS Power Other D6 VCC Power Other Table 4 4 Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Dire...

Page 67: ...in Number Pin Number Pin Name Signal Buffer Type Direction G5 VCC Power Other G6 VSS Power Other G21 VCC Power Other G22 VSS Power Other G23 VSS Power Other G24 D 22 Source Synch Input Output G25 D 17...

Page 68: ...P Power Other N22 VSS Power Other Table 4 4 Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction N23 VSS Power Other N24 D 27 Source Synch Input Output N25 D 30 Source Synch Inpu...

Page 69: ...ource Synch Input Output V25 VSS Power Other V26 D 44 Source Synch Input Output W1 A 8 Source Synch Input Output W2 A 10 Source Synch Input Output W3 VSS Power Other W4 VCCQ 1 Power Other W5 VCC Power...

Page 70: ...nput Output Address strobes are used to latch A 31 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below BCLK 1 0 Input The differential pair BCLK Bus Cloc...

Page 71: ...shows the grouping of data signals to data strobes and DINV Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the...

Page 72: ...signal from the Intel 852 855 and 915 chipset family used to reduce power on the Intel Pentium M data bus input buffers DRDY Input Output DRDY Data Ready is asserted by the data driver on each data tr...

Page 73: ...by a SHUTDOWN transaction on the FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of...

Page 74: ...hapter 5 for more details For termination requirements please refer to the platform design guides This signal may require voltage translation on the motherboard Please refer to the platform design gui...

Page 75: ...low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor...

Page 76: ...tion of decoupling on the VCCQ lines if necessary VCCSENSE Output VCCSENSE is an isolated low impedance connection to processor core power VCC It can be used to sense or measure power near the silicon...

Page 77: ...from the processor fan may also be used to cool other platform components or lower the internal ambient temperature within the system To allow for the optimal operation and long term reliability of I...

Page 78: ...4 GHz HFM Vcc 10 765 755 745 735 725 715 778 758 738 600 MHz LFM Vcc 7 5 773 1 3 GHz HFM Vcc 5 5 753 1 2 GHz HFM Vcc 5 5 733J 1 1 GHz HFM Vcc 5 5 733 1 1 GHz HFM Vcc 5 0 723 1 0 GHz HFM Vcc 5 0 773 7...

Page 79: ...2 LFM Vcc 0 9 HFM Vcc 1 7 PDSLP 765 755 745 735 725 715 Deep Sleep Power W At 35 C Note 2 LFM Vcc 2 5 HFM Vcc 8 8 778 758 738 Deep Sleep Power W At 35 C Note 2 LFM Vcc 2 5 HFM Vcc 2 9 773 753 733J Dee...

Page 80: ...f the processor has been reached When using the thermal diode a temperature offset value must be read from a processor Model Specific register MSR and applied See Section 5 1 2 for more details Please...

Page 81: ...k Boltzmann Constant and T absolute temperature Kelvin Value shown in the table is not the Pentium M Processor thermal diode ideality factor It is a reference value used to calculate the Pentium M Pro...

Page 82: ...Monitor 1 and Intel Thermal Monitor 2 These modes are selected by writing values to the Model Specific registers MSRs of the processor After Automatic mode is enabled the TCC will activate only when...

Page 83: ...ctive Besides the thermal sensor and thermal control circuit the Intel Thermal Monitor feature also includes one ACPI register one performance counter register three model specific registers MSR and o...

Page 84: ...84 Datasheet Thermal Specifications and Design Considerations...

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