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Intel

®

Pentium

®

III Processor/840 Development Kit Manual

B-1

Termination Chip for Uniprocessor
Systems

B

If the system is designed as a dual-processor system, but only one processor is implemented (for
testing purposes or for applications that require only one processor), a termination chip is required
in the unpopulated socket. The following are third-party suppliers of termination chip solutions:

FCI Electronics
Contact: Scott Beardsley
(510) 651-2700 x479
[email protected]

Methode
Contact: Jackie Muller
(708) 867-9600
[email protected]

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Summary of Contents for Pentium III Processor/840

Page 1: ...Intel Pentium III Processor 840 Development Kit Manual April 2001 Order Number 273333 003...

Page 2: ...latforms may require licenses from various entities including Intel Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your pr...

Page 3: ...3 1 3 1 Evaluation Board Block Diagram 3 1 3 2 Mechanical Design 3 2 3 3 System Operation 3 2 3 3 1 Pentium III Processor 3 2 3 3 2 On Board Voltage Regulators 3 2 3 3 2 1 Voltage Regulator Module VR...

Page 4: ...r LED Status 3 12 4 Hardware Reference 4 1 4 1 Thermal Management 4 1 4 2 In Target Probe ITP Debugger Port 4 1 4 3 Post Code Display 4 1 4 4 WTX Power Supply 4 1 4 5 PCI Expansion Slots 4 2 4 6 PCI D...

Page 5: ...lf Test POST 5 1 5 3 The BIOS User Interface 5 1 5 4 Setup Screen System 5 4 5 4 1 Basic CMOS Configuration Screen 5 4 5 4 2 Configuring Drive Assignments 5 5 5 4 2 1 Configuring Floppy Drive Types 5...

Page 6: ...Layout 3 12 5 1 BIOS POST Pre Boot Environment 5 2 5 2 Graphical POST 5 3 5 3 Embedded BIOS Setup Screen Menu 5 4 5 4 Embedded BIOS Basic Setup Screen 5 5 5 5 Embedded BIOS Custom Setup Screen 5 8 5 6...

Page 7: ...4 7 4 12 Audio Line In Connector Pinouts J1K1 4 7 4 13 Audio Line Out Connector Pinouts J1K1 4 8 4 14 MIDI Game Port Connector Pinouts J1A1 4 8 4 15 Wake On LAN Connector Pinouts J2F2 Not Populated 4...

Page 8: ...sion History Date Revision Description April 2001 003 Updated for 866 MHz Pentium III processor BOM format changed Key components BOM expanded to include all kit components April 2000 002 Updated for...

Page 9: ...erence This chapter provides a description of jumper settings and functions and pinout information for each connector Chapter 5 BIOS Quick Reference This chapter describes how to configure the BIOS fo...

Page 10: ...hat is 255 is a decimal number and 1111 1111 is a binary number In some cases the letter B is added for clarity Units of Measure The following abbreviations are used to represent units of measure A am...

Page 11: ...hnical Support In the U S and Canada technical support representatives are available to answer your questions between 5 a m and 5 p m PST You can also fax your questions to us Please include your voic...

Page 12: ...273332 VRM 8 4 DC DC Converter Design Guidelines 245335 P6 Family of Processors Hardware Developer s Manual 244001 Intel Architecture Software Developer s Manual Volume 1 Basic Architecture 243190 Int...

Page 13: ...g and operating the system 2 1 1 Baseboard Features The evaluation board features are summarized below Full support for two Intel Pentium III processors with 256 Kbytes of on die L2 Cache at up to 866...

Page 14: ...tion Plug in voltage regulator module VRM connectors In target probe ITP connector to interface to an ITP debugger Note Note the ITP connector used on this board requires a 1 5 V supply voltage Integr...

Page 15: ...oltage test points Clear CMOS jumper Single or dual processing ITP mode jumper 2 2 Included Hardware Evaluation board baseboard Two Intel Pentium III processors at 866 MHz with 133 MHz processor syste...

Page 16: ...d BIOS for the Intel Pentium III Processor 840 Development Kit The Intel Pentium III Processor 840 Development Kit ships pre installed with Embedded BIOS pre boot firmware from General Software Embedd...

Page 17: ...ate reusable components that were not included in the product i e some device drivers applications etc Once created new components can be imported into Target Designer where they can then be incorpora...

Page 18: ...lly and numerically displays performance results Collects hardware and Windows system configuration information 2 4 Before You Begin Before you set up and configure your evaluation board you may want...

Page 19: ...damaged Network Adapter An Intel 82559ER Ethernet controller is integrated into the baseboard design You may use a different network card not included in the kit however you are responsible for insta...

Page 20: ...anual Getting Started Figure 2 1 Evaluation Board Jumpers J1N1 J1N2 J1N3 J11P1 J11P2 J11P3 J11P4 J11R3 J11R2 J11R1 J2L1 J3K2 J2K1 J2J1 J3J1 J3J2 J11 J6F1 J2F2 J2F1 J7F1 J8F1 J10A1 J8G1 J8F3 J8F2 J11T1...

Page 21: ...RAMBUS ISR Front Panel I O Connectors Power Switch Reset Switch RDRAM Slots Floppy IDE1 IDE2 Post I O Fans PCI 64 66 Expansion Slots MIDI Game PCI 32 33 AGP ATAPI Audio Aux ATAPI Audio Audio Serial P...

Page 22: ...tandoff feet insert a washer onto a screw then push the screw through the top of the board From below the board thread one of the standoff feet onto the screw It is recommended that you install the mo...

Page 23: ...evaluation board Be sure to align Pin 1 of the cable connector with pin 1 of J10E1 Connect the other end of the cable to the hard disk drive Connect the power cable to the hard drive Caution Make sur...

Page 24: ...itch The red push button switch labeled S11R1 is the power switch to the baseboard Push it once to turn the power on or off Please note that when the system is powered down using the S11R1 switch the...

Page 25: ...32 33 MHz PCI 32 33 MHz VRM 8 4 VRM 8 4 DRCG CK133 WS ITP Intel Pentium III Processor Socket 370 AGP Intel Pentium III Processor Socket 370 MCH ICH AGP 4X P64H LAN 82559ER AHA_B IDE IDE AC 97 Audio Po...

Page 26: ...p Pin Grid Array FC PGA package The Pentium III processor is the next member of the P6 family in the Intel IA 32 processor line Like the Pentium II processor the Pentium III processor implements the D...

Page 27: ...rmware Hub FWH In addition to providing high performance the Intel 840 chipset was designed for scalability Three components may be used with the core components listed above The 64 bit PCI Controller...

Page 28: ...The ICH supports 32 bit PCI IDE controllers and dual USB ports The ICH is a highly integrated multifunctional I O Controller Hub that provides the interface to the PCI Bus and integrates many of the f...

Page 29: ...zed The MRH R converts each memory channel into two memory channels for expanded memory capacity MRH R has not been implemented in this evaluation board 3 3 3 6 SDRAM based Memory Repeater Hub MRH S F...

Page 30: ...N connector Single Floppy connector Serial Ports One Parallel Port Two USB Ports IDE Ports PS 2 Keyboard and mouse ports 3 3 7 AGP Connector AGP support is provided through the 82840 MCH One industry...

Page 31: ...d 82559ER LAN Controller 82559ER Features Support of Wired for Management WfM 10 100 Mbit Ethernet controller 3 3 13 Legacy I O Support for legacy I O functions is provided by the SMSC Super I O contr...

Page 32: ...board has an on board POST code display Data from any program that performs an I O write to 0080H is latched and displayed on the two LEDs U10C1 and U11C1 During BIOS startup codes are posted to thes...

Page 33: ...2 4 Serial Port 1 5 Parallel Port PNP0 option 6 Floppy 7 Parallel Port 1 8 Real Time Clock 9 IRQ2 Redirect 10 Reserved Not supported 11 Reserved Not supported 12 On board mouse port if present else u...

Page 34: ...ssor 840 evaluation board Table 3 3 ACPI 1 0 System States and Power States Global States Sleep States CPU States Device States Targeted System Power G0 S0 working state N A C0 working D0 working stat...

Page 35: ...on board and does not meet FCC regulations It is intended for use in lab environments only 3 7 Battery Requirements A Type 2032 socketed 3 V lithium coin cell battery is used on this evaluation board...

Page 36: ...are consistent with the WTX 1 02 specification 3 8 4 Back Panel I O Connector Layout The back panel I O connector layout is consistent with the WTX 1 02 specification as shown in Figure 3 2 3 9 Power...

Page 37: ...ITP Debugger Port The evaluation platform is populated with a 1 5 V In Target Probe ITP debugger port The ITP port provides a path for debugger tools like emulators in target probes and logic analyzer...

Page 38: ...umbers by connecting an address line to the IDSEL signal of each PCI device Table 4 1 shows the mapping of PCI devices 4 7 PCI64 Device Mapping Table 4 2 shows the mapping of 64 bit 66 MHz PCI devices...

Page 39: ...secondary power connector J3P1 Table 4 3 Main Power Connector Pinout J3M1 Pin Signal Name Function 1 3 3 V 3 3 V 2 3 3 V 3 3 V 3 3 3 V 3 3 V 4 3 3 V 3 3 V 5 3 3 V 3 3 V 6 GND Ground 7 GND Ground 8 GN...

Page 40: ...ection 9 Fan C No Connection 10 PS OK Voltages within acceptable ranges 11 1394 No Connection 12 5 V Rtn 5 V Sense Return 13 3 3 V Rtn 3 3 V Sense Return 14 RES No Connection 15 GND Ground 16 12 V 12...

Page 41: ...to the dual stacked USB connector J1P1 Table 4 6 ITP Debugger Connector Pinout J3K1 Pin Signal Name Pin Signal Name 1 GND 2 RESET 3 GND 4 DBRESET 5 GND 6 TCLK 7 TDI_P0 8 TMS 9 TD0_P1 10 POWERON 11 TR...

Page 42: ...e signals assigned to the parallel port connector J1L1 Table 4 8 Keyboard and Mouse Connector Pinouts J1P2 Pin Signal Name 1 Data 2 No Connect 3 GND 4 5 V fused 5 Clock 6 No Connect Table 4 9 DB25 Par...

Page 43: ...Port Connectors Table 4 11 shows the signals assigned to the audio mic in connector J1J1 Table 4 12 shows the signals assigned to the audio line in connector J1K1 top Table 4 10 Serial Port Connector...

Page 44: ...WOL connector J2F2 Table 4 16 shows the signals assigned to the RJ45 connector J1K2 Table 4 13 Audio Line Out Connector Pinouts J1K1 Pin Signal Name Sleeve GND Tip Audio Left Out Ring Audio Right Out...

Page 45: ...gnal Name 1 IO1 2 IO2 3 IO3 4 IO4 5 IO5 6 IO6 7 IO7 8 IO8 Table 4 17 Front Panel I O Connector Pinouts J12R1 Pin Signal Name Pin Signal Name 1 SW_ON 15 HD Active 2 Ground 16 HD PWR 3 NC 17 Key 4 NC 18...

Page 46: ...e Changes Between SW ON and FPPWR_ON System State Contact Closure SW_ON to Ground Result Off Any duration System Power On On 4 seconds System sleep On 4 seconds System Power Off Sleep 4 seconds System...

Page 47: ...ns two rows with twenty pins per row Table 4 24 shows the signals assigned to connectors IDE1 J10E1 and IDE2 J10F1 Table 4 22 ATAPI Audio Connector Pinouts J1H1 Pin Signal Name 1 CD Left 2 Ground 3 Gr...

Page 48: ...0 Key 40 Ground Table 4 24 IDE Connector Pinouts for IDE1 J10E1 and IDE2 J10F1 Sheet 2 of 2 Pin Signal Name Pin Signal Name Table 4 25 Floppy Drive Connector Pinouts J10F2 Pin Signal Name Pin Signal N...

Page 49: ...1B A40 SDONE B40 PERR A10 VCC B10 No Connect A41 SBO B41 3 3 V A11 No Connect B11 PRSNT2B A42 GND B42 SERR A12 GND B12 GND A43 PAR B43 3 3V A13 GND B13 GND A44 AD15 B44 CBE1 A14 No Connect B14 No Conn...

Page 50: ...NT1 56 GND AD3 10 3 3 V No Connect 57 AD2 GND 11 No Connect PRSNT2 58 AD0 AD10 12 KEY KEY 59 3 3 V 3 3 V 13 KEY KEY 60 REQ64 ACK64 14 3 3 V AUX No Connect 61 5 V 5 V 15 RST GND 62 5 V 5 V 16 3 3 V CLK...

Page 51: ...4 28 AGP Connector Pinouts Sheet 1 of 2 Pin A B Pin A B 1 12 V OVRCNT 34 3 3 Vddq 3 3 Vddq 2 TYPEDET 5 0V 35 AD22 AD21 3 Reserved 5 0V 36 AD20 AD19 4 USB USB 37 GND GND 5 GND GND 38 AD18 AD17 6 INTA I...

Page 52: ...erved AD_STB0 27 AD28 AD29 60 AD6 AD7 28 3 3 VCC 3 3 VCC 61 GND GND 29 AD26 AD27 62 AD4 AD5 30 AD24 AD25 63 AD2 AD3 31 GND GND 64 3 3 Vddq 3 3 Vddq 32 Reserved AD_STB1 65 AD0 AD1 33 C BE3 AD23 66 Rese...

Page 53: ...t J2L1 J2K1 IN 2 3 PSB 100 MHz 2 pin 1x2 Header OUT OUT PSB 133 MHz X 3 pin 1x3 Header OUT 1 2 Reserved IOQ J6R2 IN IOQ 1 2 pin 1x2 Header OUT CHIPSET X 82559 J2F1 1 2 Enable X 3 pin 1x3 Header 2 3 Di...

Page 54: ...override P1 J10 must be set to the IN position To boot the board without either processor being enabled both jumpers must be set When operating in uni processor mode the jumper need not be set to ign...

Page 55: ...jumper is installed the In Order Queue IOQ is set to 1 Otherwise the IOQ is set to 8 4 10 6 82559 Ethernet Controller Enable J2F1 This jumper is used to enable disable the 82559ER LAN Controller By de...

Page 56: ...the VID jumpers can result in permanent damage to the processor 4 10 13 P1 Voltage Regulator Module Voltage ID J11P4 J11P3 J11R3 J11R2 J11R1 The P1 VID jumpers allow the CPU s core voltage to be alte...

Page 57: ...ions of this chapter provide the BIOS POST Codes and Beep codes 5 2 Power On Self Test POST When the system is powered on Embedded BIOS tests and initializes the hardware and programs the chipset and...

Page 58: ...PCI resource assignment table Figure 5 1 shows the format of the text based POST display The display is very similar if console redirection through a COM port is used instead Figure 5 2 shows the gra...

Page 59: ...will be lost and the board will need to be reconfigured The Basic Setup Screen provides an option to disable the graphical POST and switch to the legacy text based version This feature may not permane...

Page 60: ...o advance to the next field and and keys cycle through values such as those in the Basic Setup Screen or the Diagnostics Setup Screen 5 4 1 Basic CMOS Configuration Screen The system s drive types boo...

Page 61: ...d disk assignments The first floppy should be A and the first hard drive should be C Also do not assign the same file system to more than one drive letter Thus Floppy0 should not be used for both A an...

Page 62: ...A is now in common use Physical This type instructs the BIOS to query the drive s geometry from the controller on each POST No translation on the drive s geometry is performed so this type is limited...

Page 63: ...to the boot process from the debugger environment type G at the debugger prompt and press ENTER MFGMODE Initiate Manufacturing Mode allowing the system to be configured remotely via an RS232 connect...

Page 64: ...ective enabling and disabling of shadowing in 16 Kbyte sections except for the top 64 Kbytes of the BIOS ROM which is shadowed as a unit Normally shadowing should be enabled at C000 C400 to enhance VG...

Page 65: ...r is encountered Caution The disk I O diagnostics perform write operations on those drives therefore only spare drives should be used which do not contain data that could be harmed by the test Caution...

Page 66: ...t target hardware A full discussion of the uses of Manufacturing Mode is beyond the scope of this chapter Complete documentation and host side software is available directly from General Software For...

Page 67: ...through the Basic CMOS Configuration Setup Screen to boot the NK BIN file from the boot drives instead of the boot records on those drives To configure your system to boot Windows CE natively from a...

Page 68: ...will still be waiting for its command and will not prompt again until you press ENTER again The debugger can also be entered from the Setup Screen System and as a boot activity see Basic CMOS Configu...

Page 69: ...P command POST_STATUS_SHUTTEST 0dh Test CMOS RAM shutdown register POST_STATUS_CMOSDIAG 0eh Check CMOS checksum POST_STATUS_CMOSINIT 0fh Initialize CMOS contents POST_STATUS_CMOSSTATUS 10h Initialize...

Page 70: ...d high memory size from patterns POST_STATUS_CHECKSEG40B 4ah Verify ROM BIOS data area again POST_STATUS_CHECKDEL 4bh Check for DEL pressed POST_STATUS_CLREXTMEM 4ch Clear extended memory for soft res...

Page 71: ...TUS_POSTC8000 98h ROM C800h extension returned POST_STATUS_TIMERPRNBASE 99h Configure timer printer data POST_STATUS_SERIALBASE 9ah Configure serial port base addresses POST_STATUS_INITBEFORENPX 9bh P...

Page 72: ...CountDescription of Problem POST_BEEP_REFRESH 1 Memory refresh is not working POST_BEEP_PARITY 2 Parity error found in 1st 64KB of memory POST_BEEP_BASE64KB 3 Memory test of 1st 64KB failed POST_BEEP...

Page 73: ...rocessors To do this remove the fans from each processor Lift the bar on the side of the PGA370 sockets to release the processors Carefully lift the processors out of their sockets 4 Install the 100 M...

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Page 75: ...processor is implemented for testing purposes or for applications that require only one processor a termination chip is required in the unpopulated socket The following are third party suppliers of te...

Page 76: ......

Page 77: ...ire PRE_LED 1 0 wire pre_LSERR_N wire PRE_LO_OUT 6 0 wire PRE_HI_OUT 6 0 wire dlad dff control dff dout dff data_low 3 0 dff data_high 3 0 dff hex machine with states my_reset IDLE ADDR3 ADDR2 ADDR1 A...

Page 78: ...PNDRN PRE_HI_OUT 1 HI_OUT 0 OPNDRN PRE_HI_OUT 0 ADDED TO CONTROL FLASHING ACPI LEDS BWF 11 18 98 Removed 6 23 for Tioga B0 LED_SEL 1 SLP_S3 LED_SEL 0 SLP_S5_N LED_S3 PRE_LED 1 LED_S5 PRE_LED 0 CASE LE...

Page 79: ...1001111 WHEN H 4 PRE_HI_OUT 6 0 B 1100110 WHEN H 5 PRE_HI_OUT 6 0 B 1101101 WHEN H 6 PRE_HI_OUT 6 0 B 1111101 WHEN H 7 PRE_HI_OUT 6 0 B 0000111 WHEN H 8 PRE_HI_OUT 6 0 B 1111111 WHEN H 9 PRE_HI_OUT 6...

Page 80: ...ycle is i o write cycle else hex my_reset i o read cycle OR start of a cycle but cycle is not i o cycle end if else hex my_reset LFRAME_N went high but not start MAy be reserved bus master grant etc e...

Page 81: ...3 0 data_high 3 0 data_high 3 0 when DIN_LOW if LFRAME_N gnd THEN hex my_reset else hex DIN_HIGH next phase of latching data end if control gnd DOUT DOUT dummy data_low 3 0 LAD 3 0 data_high 3 0 data...

Page 82: ...igh 3 0 when TAROUT1 if LFRAME_N gnd THEN hex my_reset else hex TAROUT2 same flow for read write end if control gnd DOUT DOUT data_low 3 0 data_low 3 0 data_high 3 0 data_high 3 0 when TAROUT2 if LFRA...

Page 83: ...2 C9E2 C9E3 C9H1 C9H3 C9H5 C9J1 C9J3 C9J6 C9M2 C9M3 C9N2 C9P3 C9P4 C10M6 C10 M7 C10P1 C10P2 C10P4 SMC103P_0603 0 01U SMC0603 50V KEMET C0603C103K3RAC KEMET C0603C103J5RAC C1D1 C4P2 C4P3 C5L6 C5L7 C7E1...

Page 84: ...RM39COG220J050A C2H8 SMC8_20_0805 8 2P SMC0805 50V MURATA GRM40COG8R2C050 AD C2L1 C2M1 C3F3 C3F7 C4H2 C6J1 C 8G3 C8G4 C8J3 C9J4 C9M1 C9M5 C 9P2 C10H1 C10J1 C10M9 C10P3 C11 M2 C7L5 SMC226P_T6032 22UF S...

Page 85: ...1J1 FB1J2 FB1K1 FB1K2 F B1P1 FB30OHM3A 30_OHM SMF0805 MURATA BLM21P300SPT FB2P1 FB2P2 FB3L1 FB4K1 FB8K1 F B9J1 FB60OHM6A 60_OHM SMF1806 MURATA BLM41P600SPT1 FP1P1 FP1P2 ACA3216M4 060 60_OHM SMFA1206 T...

Page 86: ...OROLA MMBT2222ALT1 Q4J1 Q4P1 Q5M1 Q8G1 Q9G1 Q11K 1 EZ1585CM TO263F1 SEMTECH EZ1585CM SEMTECH EZ1585ACM Q5F1 Q5F2 MOSFETN SOI8 SILICONIX SI4410DY T Q7R1 FDV301N SOT23 FAIRCHILD FDV301N Q8J1 Q8J2 Q8K1 Q...

Page 87: ...7K SMR0805 ROHM MCR10EZH473 R4J1 R4N2 SMR5_112_805 511 SMR0805 ROHM MCR10EZHF5110 R4K1 R4K2 R4R1 R4R2 SMR2_672_805 267 SMR0805 ROHM MCR10EZHF2670 R4M1 R7T1 R29 R32 SMR3_32_603 330 SMR0603 ROHM MCR03EZ...

Page 88: ...EZHF5620 ROHM MCR10EZHF56520 R9G3 R10J3 SMR1_622_805 162 SMR0805 ROHM MCR10EZHF1620 R9J2 SMR1_53_805 15K SMR0805 ROHM MCR10EZH153 R11E1 R11F1 R12T1 SMR4_72_805 470 SMR0805 ROHM MCR10EZH471 R11M6 R11R1...

Page 89: ...001 DB DBX 05A RDI DMT 1206 RDI DMT 1206 I CHALLENGE ELECTRONICS DBX 05A TH1A1 THRMSTR1_1A 1 1AMP SMRT1812 RAYCHEM CO Mini SMDC 110 2 TH2P1 THRMSTR 1 1AMP SMRT1208 RAYCHEM CO SMD100 2 TH2P2 THRMSTR2_5...

Page 90: ...4LVC32D U12L1 U12L2 74HC04 SOI14 MOTOROLA MC74C04AD U12M1 74LVC14D SOI14 PHILIPS SN74LVC14D PHILIPS SN74LVC14A D U12M2 74LVC08 SOI14 TEXAS INST SN74LVC08D U12N1 SN74F07 SOI14 SIGNETICS N74F07D Y1E1 XT...

Page 91: ...2 Agilent Technologies Arcti Cooler HACA 0001 400MHZ RIMM PC 800 Qty 2 Samsung KMMR18R84AC1 RK8 Continuity Module CRIMMs Qty 2 Samsung KMMR18CNTY1 Glue Chip Mitel GSC90031 BIOS Flash Memory 8Mbit Int...

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Page 93: ...Processor ITP VRM MCH 1 MCH 2 MCH 3 MCH Support Clock Distribution Clock Generation DRCG RIMM CHA Connectors RIMM CHB Connectors RIMM CHA Term Decoupling RIMM CHB Term Decoupling Power Management Map...

Page 94: ...P64H PCI64 Slot 1 PCI64 Slot 2 PCI64 Pullups and Decoupling Ethernet 82559ER Ethernet 82559ER Connector and Decoupling IDE USB FWH LPC Gameport Floppy KBD Mouse Serial Parallel Ports Front Panel I O...

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Page 96: ...G port 80 LED FWH LAN DRCG 82559 MCH VRM VRM 8 4 8 4 AGP 4X IDE SuperI O PCI 64 66Mhz PCI 64 66Mhz PCI 64 I T P RAMBUS CHA RAMBUS CHB FC PGA 370 FC PGA 370 82840 ICH 82801 82806 P64H AHA B AHA A CK133...

Page 97: ...Place inside the center of the socket Place around to socket Place one 820u close to VRM...

Page 98: ...Place one 820u close to VRM Place around the socket Place inside the center of the socket...

Page 99: ...P T I P0 P1 Remove resistors and To enable PSMI stuff jumper blocks FOR UNI PROCESSOR OPERATION ITP DIAGRAM TERMINATION CARD MUST ROUTE TDI TDO...

Page 100: ...2 3 0 1 2 No jumper Jumper position CPU VID 4 0 1 VRM VID 4 0...

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Page 103: ...FSB ECC CONTROL IN ECC ENABLED...

Page 104: ...IOQ DEPTH SELECTION 1 CHIPSET ICH HUBREF GENERATION Place close to MCH Place close to MCH HOST BUS MCH GTLREFA GENERATION Place close to MCH MCH GTLREFB GENERATION FREQUENCY STRAP MCH DECOUPLING RAMB...

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Page 106: ...external clock and stuff connector remove crystal close Place FSB Select to CK133 Zero ohm series nets are AC Terminated at the loads Install 33ohm for series termination and remove destination resist...

Page 107: ...1 1 1 50 6 100 100 133 50 6 400 FSB RAMBUS RATIO MULT1 MULT0 DRCG_REF_CLK 66 5 0 1 RAMBUS FREQUENCY SELECTION 0 1 0 S0 Output Enable Test Bypass Normal S1 Test 50 0 0 4 200 50 1 0 8 400 66 5 1 0 8 53...

Page 108: ...close Place to RIMM...

Page 109: ...to RIMM close Place...

Page 110: ...RAMBUS SUS1 8V GENERATION RIMM DECOUPLING RAMBUS VREF GENERATION one 0 1uF cap per 2 RSL lines TERMINATION DECOUPLING Back No Stuff Decouple...

Page 111: ...RAMBUS SUS1 8V GENERATION TERMINATION DECOUPLING RIMM DECOUPLING one 0 1uF cap per 2 RSL lines Back No Stuff Decouple RAMBUS CHB VREF GENERATION...

Page 112: ...AMP AD1881 AUDIO CMOS PULLUPS CK133 DRCG ITP CLK BUFFER VCC3_3 AGP1_5 AGP MCH RIMMs Note Only major devices are listed in this diagram CPUs AGP 2 5V MCH DRCG ICH P64H MIC AMP PCI64 AGP PCI32 PCI64 FWH...

Page 113: ...GTL Vtt 1 5V Vref 2 3 Vtt RSL Vtt 1 8V Vref 2 3 Vtt AGP Vdd 1 5V or 3 3V Vref 0 5 Vagpdd 1 5V or 0 4 Vagpdd 3 3V AHA Vdd 1 8V Vref 0 5 Vdd...

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Page 118: ...Place close to P1 Place close to P0...

Page 119: ...WAKE ON LAN HEADER WTX CHASSIS EXHAUST HEADDERS WTX IO HEADDERS P1 FAN HEADER P0 FAN HEADER...

Page 120: ...Keep trace stub for STROBE pullups under 0 1 inch Keep trace stub for all pullups under 0 5 inch close to pullups Place close to MCH VREFGC generation for 3 3V AGP cards Place these caps AGP DECOUPLIN...

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Page 122: ...e 2 3 1 2 NORMAL CLEAR CMOS IN OUT Use CPU freq strap in ICH Force safe mode 1111 No reboot on 2nd watchdog timeout Reboot on 2nd watchdog timeout CMOS jumper close to ICH Place pads Strap options clo...

Page 123: ...MCH HUBREF GENERATION Place close to ICH ICH DECOUPLING RTC BATTERY...

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Page 132: ...Place close to P64H Rpack Decouple P64H HUBREF GENERATION...

Page 133: ...2 3 1 2 82559 EN DIS ENABLE DISABLE...

Page 134: ...signal Create termination plane in PCB as close to the 82559 as possible Keep termination resistors for this Use plane...

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Page 136: ...to ICH close Place to ICH Place close...

Page 137: ...TBL jumper Remove in FAB B OUT IN UNLOCKED LOCKED...

Page 138: ...Place close to the power pins...

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Page 140: ...Place RC networks close to the connector...

Page 141: ...On board speaker jumper 26 27 Front panel speaker connect to 24 27 S3 STATE INDICATOR S5 STATE INDICATOR S0 S1 STATE INDICATOR ACPI STATE LED INDICATORS...

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Page 148: ...ents 5 Integrated BIOS debugger 11 Setup Screen System 3 Shadow Configuration Setup Screen 8 Standard Diagnostics Routines Setup Screen 9 Board dimensions 11 Board layout 12 BOM 1 Boot ROM 6 C CD ROM...

Page 149: ...l conventions 2 O Online help 3 P P0 Voltage Regulator Module Voltage ID 20 P1 Voltage Regulator Module Voltage ID 20 P1 P0 Present Override 18 Parallel Port Connector 6 PCI 32 Connector 6 13 PCI 32 s...

Page 150: ...ration 7 Units of measure defined 2 Universal Serial Bus 2 USB Connector 5 USB Port 7 V VGA monitor 6 Video adapter 3 6 Voltage regulator module 2 3 Voltage regulators 2 W Wake On LAN WOL connector 8...

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