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28

80960SA

4.0

WAVEFORMS

Figures 17, 18, 19, 20 and 21 show waveforms for various transactions on the 80960SA’s bus. Figure 22 shows
a cold reset functional waveform.

Figure 17. Non-Burst Read and Write Transactions Without Wait States

T

a

T

d

T

r

T

a

T

d

T

r

CLK2

CLK

ALE

AS

A31:16

W/R

DT/R

DEN

READY

BLAST

BE1:0

VALID

VALID

INVALID

A3:1

ADDR

ADDR

DATA

D

A15:4,
D15:0

VALID

VALID

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Summary of Contents for 80960SA

Page 1: ...ers Figure 1 The 80960SA Processor s Highly Parallel Architecture Relative to Digital Equipment Corporation s VAX 11 780 at 1 MIPS VAX 11 is a trademark of Digital Equipment Corporation High Performan...

Page 2: ...t in Testability 7 1 1 12 CHMOS 7 2 0 ELECTRICAL SPECIFICATIONS 11 2 1 Power and Grounding 11 2 2 Power Decoupling Recommendations 11 2 3 Connection Recommendations 11 2 4 Characteristic Curves 11 2 5...

Page 3: ...tates 28 Figure 18 Quad Word Burst Read Transaction With 1 0 0 0 0 0 0 0 Wait States 29 Figure 19 Burst Write Transaction With 2 1 1 1 Wait States 6 8 Bytes Transferred 30 Figure 20 Accesses Generated...

Page 4: ......

Page 5: ...gns All members of the i960 processor family share a common core architecture which utilizes RISC technology so that except for special functions the family members are object code compatible Each new...

Page 6: ...iminate the instruction alignment stage in the pipeline To simplify the instruction decoder there are only five instruction formats each instruction uses only one format See Figure 3 5 Overlapped Inst...

Page 7: ...can Over Bit Extract Modify Comparison Branch Call Return Fault Compare Conditional Compare Compare and Increment Compare and Decrement Unconditional Branch Conditional Branch Compare and Branch Call...

Page 8: ...12 Bit Offset 32 Bit Offset Register Indirect Register 12 Bit Offset Register 32 Bit Offset Register Index Register x Scale Factor Register x Scale Factor 32 Bit Displacement Register Index Register...

Page 9: ...many calls deep a program typically oscillates back and forth between only two to three levels As a result with four stack frames in the cache the proba bility of having a free frame available on the...

Page 10: ...he register contents as shown in the following example ld data_2 r4 ld data_2 r5 Unrelated instruction Unrelated instruction add r4 r5 r6 In essence the two unrelated instructions between LOAD and ADD...

Page 11: ...r and necessary state information to make efficient recovery possible Like interrupt handling routines fault handling routines are usually written to meet the needs of specific applications and are of...

Page 12: ...g a hold cycle Th AS O T S ADDRESS STATUS indicates an address state AS is asserted every Ta state and deasserted during the following Td state AS is driven HIGH during reset W R O T S WRITE READ spec...

Page 13: ...erforms a self test If the self test completes successfully FAIL is deasserted The processor then performs a zero checksum on the first eight words of memory If it fails FAIL is asserted for a second...

Page 14: ...n asserted for at least one additional bus cycle In an asynchronous system the pin must remain deasserted for at least two system clock cycles and then asserted for at least two more system clock cycl...

Page 15: ...Inductance is reduced by shortening board traces between the processor and decoupling capacitors as much as possible 2 3 Connection Recommendations For reliable operation always connect unused inputs...

Page 16: ...rent vs Frequency Room Temp VCC 5 0V POWER SUPPLY CURRENT mA CASE TEMPERATURE C 20 MHz 16 MHz 10 MHz 100 150 200 250 300 350 10 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 OPERATING FREQUENCY...

Page 17: ...0 Figure 9 Capacitive Derating Curve 0 20 40 60 80 100 30 25 20 15 10 THREE STATE OUTPUT CAPACITIVE LOAD pF TEMP 85 C VCC 4 5V 5 0 RISING FALLING X X X VALID DELAY NS 2 5 Test Load Circuit Figure 10...

Page 18: ...MHz PLCC TCASE 0 C to 85 C VCC 5V 10 80960SA 20 MHz PLCC TCASE 0 C to 85 C VCC 5V 5 Table 5 DC Characteristics Symbol Parameter Min Max Units Notes VIL Input Low Voltage 0 3 0 8 V VIH Input High Volta...

Page 19: ...clock CLK2 which should be tested with input voltages of 0 45V and 0 7 x VCC See Figure 11 and Tables 6 7 and 8 for timing relationships for the 80960SA signals Figure 11 Drive Levels and Timing Relat...

Page 20: ...8 ALE Output Valid Delay 4 33 ns T9 Output Float Delay 2 20 ns 2 Synchronous Inputs T10 Input Setup 1 10 ns T11 Input Hold 2 ns T12 Input Setup 2 13 ns T13 Setup to ALE Inactive 10 ns T14 Hold after A...

Page 21: ...T8 ALE Output Valid Delay 2 22 ns T9 Output Float Delay 2 20 ns 2 Synchronous Inputs T10 Input Setup 1 10 ns T11 Input Hold 2 ns T12 Input Setup 2 13 ns T13 Setup to ALE Inactive 10 ns T14 Hold after...

Page 22: ...8 ALE Output Valid Delay 2 18 ns T9 Output Float Delay 2 17 ns 2 Synchronous Inputs T10 Input Setup 1 7 ns T11 Input Hold 2 ns T12 Input Setup 2 13 ns T13 Setup to ALE Inactive 10 ns T14 Hold after AL...

Page 23: ...Timing HIGH LEVEL MIN 0 7VCC LOW LEVEL MAX 0 8V T1 T3 T5 T4 T2 90 10 1 5 V CLK2 CLK RESET OUTPUTS A B C D A B C T15 T16 INT0 INT1 INT3 LOCK INITIALIZATION PARAMETERS T17 NOTE Initialization parameters...

Page 24: ...20 80960SA Figure 14 HOLD Timing Th Th Th CLK2 CLK HOLD HLDA T12 T11 T6 T6...

Page 25: ...It is recom mended that you include separate power and ground planes in your circuit board for power distribution Pins identified as NC No Connect should never be connected Figure 15 80 Lead EIAJ Quad...

Page 26: ...A1 A2 A3 D0 W R READY DT R BE0 BE1 V SS LOCK DEN NC NC V SS V SS NC V CC V CC 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 1...

Page 27: ...A16 27 AD4 47 INT1 67 READY 8 VCC 28 AD3 48 INT2 INTR 68 A31 9 VSS 29 AD2 49 INT3 INTA 69 A30 10 AD15 30 AD1 50 HLDA 70 A29 11 AD14 31 D0 51 VCC 71 A28 12 VCC 32 VSS 52 VSS 72 VSS 13 VSS 33 VCC 53 HO...

Page 28: ...A24 79 INT1 47 VSS 13 AD5 26 A25 76 INT2 INTR 48 VSS 22 AD6 25 A26 75 INT3 INTA 49 VSS 24 AD7 20 A27 74 LOCK 58 VSS 32 AD8 19 A28 71 NC 39 VSS 37 AD9 18 A29 70 NC 63 VSS 43 AD10 17 A30 69 READY 67 VSS...

Page 29: ...A1 70 LOCK 8 A24 29 AD8 50 NC 71 VCC 9 A23 30 AD7 51 BE1 72 VSS 10 A22 31 VCC 52 BE0 73 VCC 11 A21 32 VSS 53 VCC 74 VSS 12 A20 33 VCC 54 VSS 75 NC 13 A19 34 VSS 55 CLK2 76 AS 14 A18 35 AD6 56 RESET 77...

Page 30: ...24 8 INT3 INTA 60 VCC 73 AD4 37 A25 5 LOCK 70 VSS 18 AD5 36 A26 4 NC 2 VSS 22 AD6 35 A27 3 NC 23 VSS 32 AD7 30 A28 83 NC 42 VSS 34 AD8 29 A29 82 NC 50 VSS 43 AD9 28 A30 81 NC 65 VSS 48 AD10 27 A31 80...

Page 31: ...0 50 100 200 400 600 800 Junction to Ambient Case measured in the middle of the top of the package No Heatsink 59 57 54 50 44 40 38 Junction to Case 11 11 11 11 11 11 11 NOTES This table applies to 80...

Page 32: ...actions on the 80960SA s bus Figure 22 shows a cold reset functional waveform Figure 17 Non Burst Read and Write Transactions Without Wait States Ta Td Tr Ta Td Tr CLK2 CLK ALE AS A31 16 W R DT R DEN...

Page 33: ...Word Burst Read Transaction With 1 0 0 0 0 0 0 0 Wait States Ta Tw Td Td Td Td Td Td Td Td Tr CLK2 CLK ALE AS BE1 0 W R DT R DEN READY BLAST D D D D D D D D A3 1 A15 4 D15 0 A31 16 VALID 000 001 010...

Page 34: ...e Transaction With 2 1 1 1 Wait States 6 8 Bytes Transferred Ta Tw Tw Td Tw Td Tw Td Tw Td Tr CLK2 CLK ALE AS BE1 0 W R DT R DEN READY BLAST A3 1 A15 4 D15 0 A31 16 VALID ADDR DATA DATA DATA DATA VALI...

Page 35: ...ligned One Byte from Quad Word Boundary 1 0 0 0 0 0 0 0 Wait States T a T w T d Td Td T d T d T d T d T d T r CLK2 CLK ALE AS BE1 W R DT R DEN BLAST A3 1 A15 4 D15 0 A31 16 VALID ADDR T a T w T d T r...

Page 36: ...32 80960SA Figure 21 Interrupt Acknowledge Cycle CLK2 Ta Td Tr Ti Ti Ti Ti Ti Ta Tw Td Tr A15 4 ALE AS INTA DT R DEN LOCK CLK W R BLAST A31 16 D15 0 ADDR ADD DATA A3 1 1 1 0 BE1 0 READY 1 0 1 0...

Page 37: ...D15 0 BE1 0 W R INT0 INT1 INT3 LOCK I VCC and CLK2 stable to RESET high minimum 41 CLK2 periods Initialization parameters set up to first A edge minimum 4 CLK2 periods First Bus Activity Internal sel...

Page 38: ...eristics pg 14 001 IOL value at 0 45V improved WAS 2 5 mA IS 4 0 mA LOCK pin IOL value at 0 45V relaxed WAS 12 mA IS 6 mA LOCK pin IOL value at 0 60V deleted 80960SA 16 MHz QFP added to product list 3...

Page 39: ...80960SA PLCC Pinout In Pin Order pg 26 004 JA and JC increased to reflect smaller die size and lower ICC The sections significantly changed between revisions 003 and 004 of the 80960SA SB Data Sheet w...

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