19
80960SA
Figure 12. Processor Clock Pulse (CLK2)
Figure 13. RESET Signal Timing
HIGH LEVEL (MIN) 0.7V
CC
LOW LEVEL (MAX) 0.8V
T
1
T
3
T
5
T
4
T
2
90%
10%
1.5 V
CLK2
CLK
RESET
OUTPUTS
A
B
C
D
A
B
C
T
15
T
16
INT0, INT1,
INT3, LOCK
INITIALIZATION PARAMETERS
T
17
NOTE: Initialization parameters must be set up at least four CLK2 periods before the first CLK2 “A” edge.