17
80960SA
Table 7. 80960SA AC Characteristics (16 MHz)
Symbol
Parameter
Min
Max
Units
Notes
Input Clock
T
1
Processor Clock Period (CLK2)
31.25
125
ns
V
IN
=
1.5V
T
2
Processor Clock Low Time (CLK2)
8
ns
V
T
= 10% Point
=
V
CL
+ (V
CH
– V
CL
) x 0.1
T
3
Processor Clock High Time
(CLK2)
8
ns
V
T
= 90% Point
=
V
CL
+ (V
CH
– V
CL
) x 0.9
T
4
Processor Clock Fall Time (CLK2)
10
ns
V
T
= 90% to 10% Point (1)
T
5
Processor Clock Rise Time (CLK2)
10
ns
V
T
= 10% to 90% Point (1)
Synchronous Outputs
T
6
Output Valid Delay
2
25
ns
T
6AS
AS Output Valid Delay
2
21
ns
T
7
ALE Width
T
1
- 11
ns
T
8
ALE Output Valid Delay
2
22
ns
T
9
Output Float Delay
2
20
ns
(2)
Synchronous Inputs
T
10
Input Setup 1
10
ns
T
11
Input Hold
2
ns
T
12
Input Setup 2
13
ns
T
13
Setup to ALE Inactive
10
ns
T
14
Hold after ALE Inactive
8
ns
T
15
RESET Hold
3
ns
(3)
T
16
RESET Setup
5
ns
(3)
T
17
RESET Width
1281
ns
41 CLK2 Periods Minimum
NOTES:
1. Processor clock (CLK2) rise time and fall time are not tested.
2. A float condition occurs when the maximum output current becomes less than I
LO
. Float delay is not tested, but should be
no longer than the valid delay.
3. Meeting RESET setup and hold times is an optional method of synchronizing your clocks. If you decide to use an asyn-
chronous reset, synchronizing the clock can be accomplished by using AS.
