Intel740™ Graphics Accelerator Design Guide
3-7
3 Device AGP MotherBoard Design
3.1.5.1
Signal Quality and Timing Issues
There are two modes of operation for the AGP bus, each with it's own signal quality and timing
issues. These two operating modes are 1X mode and 2X mode. Because 1X mode is a common
clock mode, flight time of the signal is of the most importance. Both minimum and maximum
flight time must be verified. The quality of the signal will also effect the flight time and therefore
must also be taken into consideration.
In AGP 2X mode operation the two major areas of concern for signaling are timing skew between
the data group signals and their associated strobe signals, and the signal quality of these signals.
The skew in a AGP 2X mode bus is comprised of elements that include crosstalk, settling time,
component loading differences, and line length differences. Bus topology effects all the above
mentioned factors of signal skew except component loading differences.
Signal quality issues may also arise from the nature of the 3-load bus topology. These signal quality
issues are caused by the loading and reflections inherent in this topology. Signal quality problems
can effect timing and skew by violating edge quality, ringback, and overshoot criteria.
The topology of the logical point-to-point bus only makes these signal quality and timing issues
worse since this type of bus contains signal loading from the third device located somewhere in the
middle of the bus and the addition of trace stubs in the bus. The loading and trace stubs create a
complex allowable routing topology with regard to trace length and component placement. Careful
simulation of the bus topology is mandatory to verify proper operation of the AGP system. Both
the case where an add-in card is present in the system and the case where the add-in card is not in
the system must be evaluated for a complete solution. Depending on how the system is designed
the bus will become balanced or unbalanced depending on the add-in card being in or out of the
system. Specific design issues faced in implementing a logical point-to-point bus will be discussed
in detail in the following sections of this document.
3.1.5.2
Strobe Edge Quality Issues
Due to the high speed nature of 2X mode AGP transfers, an AGP bus design must take into account
all aspects of edge and signal quality. Areas of signal quality concern are edge quality, ringback,
overshoot, and settling time.
Since the strobe signals act like clocks in 2X mode, their edge signal quality is paramount. Any
nonmonotonic signal edges or ledges (steps) occurring in the switching region may cause double
clocking or erratic behavior in the input buffer. Nonmonotonic edges and steps in the signal edge
while not in the switching region will add to the flight time on the strobe signal and may increase
the strobe to data group skew. This added skew may cause the system to fail. The switching region
for 2X mode ranges from Vil (0.3Vddq) to Vih (0.5Vddq) centered around a switch point of
0.4Vddq.
Rising and falling edge ringback may also cause double clocking on strobe signals if these
ringback levels are large enough. Ringback is analogous to Noise margins. When a noise margin is
negative the signal requirements are not met and double clocking could occur. The violation
criteria for strobe signal ringback is the same as the above edge quality region. Rising edge
ringback may not go below Vih (0.5Vddq), and falling edge ringback may not exceed Vil
(0.3Vddq).
See the section on Sensitivity Analysis later in this document for a full explanation of signals
quality measurements.
Summary of Contents for 740
Page 1: ...Intel740 Graphics Accelerator Design Guide August 1998 Order Number 290619 003 ...
Page 9: ...1 Introduction ...
Page 10: ......
Page 13: ...2 Intel740 Graphics Accelerator Addin Card Design ...
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Page 40: ...Addin Card Design 2 26 Intel740 Graphics Accelerator Design Guide ...
Page 57: ...3 Intel740 Graphics Accelerator 3 Device AGP Motherboard Design ...
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Page 86: ...3 Device AGP MotherBoard Design 3 28 Intel740 Graphics Accelerator Design Guide ...
Page 128: ...4 Thermal Considerations ...
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Page 131: ...Thermal Considerations 4 2 Intel740 Graphics Accelerator Design Guide ...
Page 132: ...5 Mechanical Information ...
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Page 139: ...Mechanical Information 5 6 Intel740 Graphics Accelerator Design Guide ...
Page 140: ...6 Third Party Vendors ...
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Page 144: ...A Application Notes ...
Page 172: ...Intel740 Graphics Accelerator Thermal Design Considerations 24 Application Note 653 ...
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Page 185: ...B Reference Information ...
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Page 187: ...PC SGRAM Specification Revision 0 9 February 1998 Order Number Not Applicable ...