Intel 740, Design Manual

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Revision 0.91
17
SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
8.1 Clock Routing and Chip Selects
Clock and chip select loading is two loads per line, maximum. Routing should be performed using
a T-topology, as shown below:
The following table lists the allowable stub lengths for the clock and chip select routing.
Figure 9. T-Topology Clock Routing
A 0 0 8 . v s d
b
c
a
o
o
Table 6. Stub Lengths (Clock and Chip Select Routing)
SDRAM/SGRAM Clock Frequency
Parameters 15 nS 12 nS 10 nS 8 nS Units
Min. Max Min. Max Min. Max Min. Max
a 75 150 75 150 75 150 75 150 pS
b 0 115 0 115 0 115 0 115 pS
c 0 115 0 115 0 115 0 115 pS
b+c 0 225 0 225 0 225 0 225 pS
Total Length
(clock)
100 365 175 325 175 325 175 325 pS
Total Length
(chip select)
0 365 0 365 0 365 0 365 pS