Intel 740 Design Manual Download

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Addin Card Design

2-20

Intel740™ Graphics Accelerator Design Guide

2.2.6.7

TV Out Interface

The TV out bus is the group of signals that carry digitized display data from the Intel740

graphics accelerator

to the Bt869 flicker filter TV-out component. This interface is shared with

the BIOS interface.

Table 2-12

gives the maximum trace lengths between components.

2.2.6.8

Analog Signals

It is recommended that all analog signal traces be 75

Ω

±5%. It is important that these traces not

violate the 5x10 mil spacing for the 65

Ω

traces. Analog traces include the DAC R, G, B traces, all

of the inputs to the Bt829B component and outputs from the Bt869 component.

2.2.7

UL and FCC Considerations

Certain precautions should be taken in the design of the of a graphics card to ensure passing safety
and EMI tests. These precautions are listed below.

•

When a signal can be hot plugged, clamping diodes should be used to limit voltage spikes.

•

When a voltage leaves the card, a fuse should be placed in the path to protect from a short
circuit.

•

Sockets, Fans and Brackets should be grounded.

•

Separate Power Planes of the same voltage should be stitched together.

Table 2-12. TV Out/ROMA Trace Lengths (See Figure 2-22)

Signal

Intel740™ to BIOS

Stub

BIOS Stub

BIOS to Bt869

Min

Max

Min

Max

Min

Max

ROMA[17:0]

0.0”

3.5”

0.0”

1.5”

0.0”

4.0”

Figure 2-22. Layout Dimensions, Digital TV Bus

Intel740

0.0” - 3.5”

BIOS ROM

0.0” - 4.0”

0.0” - 1.5”

Bt869

Intel740™

Chip

Summary of Contents for 740

Page 1: ...Intel740 Graphics Accelerator Design Guide August 1998 Order Number 290619 003 ...

Page 2: ...t your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order The Intel740 graphics accelerator may contain design defects or errors known as errata which may cause the products to deviate from published specifications Such errata are not covered by Intel s warranty Current characterized errata are available upon request I2C is a two ...

Page 3: ... 3 2 Ground Connections 2 9 2 2 3 3 Power Connections 2 9 2 2 3 4 Decoupling 2 10 2 2 3 5 General Signal Routing 2 11 2 2 4 Voltage Regulator 2 11 2 2 5 Bt829 Video Decoder 2 11 2 2 5 1 Ground Planes 2 12 2 2 5 2 Power Planes 2 12 2 2 5 3 Passive Components and Signal Routing 2 12 2 2 6 Bt869 Video Encoder 2 12 2 2 6 1 Ground Planes 2 12 2 2 6 2 Power Planes 2 13 2 2 6 3 Passive Components and Sig...

Page 4: ...ut and Routing 3 12 3 2 3 2 Data and strobe definitions 3 13 3 2 3 3 Assumptions for Board Design Guidelines 3 14 3 2 3 4 Add in Card guideline assumptions 3 14 3 2 3 5 Motherboard Guideline Assumptions 3 14 3 2 3 6 3 Load AGP Topology 3 16 3 2 3 7 Overall Solution Space 3 16 3 2 4 Intel740 Graphics Accelerator Memory Layout and Routing Guidelines 3 18 3 2 4 1 3 Device AGP Intel740 Graphics Accele...

Page 5: ...gital TV Bus 2 20 2 23 512Kx32 and 256Kx32 Pinout Compatibility 2 24 2 24 1M X 16 Pinout Compatibility 2 24 3 1 Pentium II Processor Intel 440BX AGPset Intel 740 Graphics Accelerator System Block Diagram 3 3 3 2 The Schematic Diagram for GPO27 PCIRST System Reset RESET ROMA16 Signals 3 4 3 3 The Schematic Diagram for the WEB SCASB SRASB CS0B CS1B and TEST 3 5 3 4 Intel740 Graphics Controller On Bo...

Page 6: ...6Kx32 Pinout Compatibility 3 26 3 23 1M X 16 Pinout Compatibility 3 26 5 1 Mounting Hole Locations Fan Heatsink Assembly 5 1 5 2 VMI Header Placement 5 2 5 3 DVD Daughter Card Dimensions ATX and NLX Top Side 5 2 5 4 50 Pin Video Connector Schematic 5 3 5 5 Recommended Bracket Placement 5 4 5 6 Recommended Bracket Cutout 5 4 ...

Page 7: ...gure 2 22 2 20 2 13 GPIO Functions 2 21 3 1 State of Signals to be Driven After System Reset but at Least One Clock Prior to Asserting TEST 3 4 3 2 Signal Duration of the GPO Signals from PIIX4 3 5 3 3 Data and Associated Strobe 3 13 3 4 Data Signal and Strobe Guideline Assumptions 3 14 3 5 Control and Clock Signal Guideline Assumptions 3 14 3 6 Data signal and strobe requirements 3 14 3 7 Control...

Page 8: ... 2 14 Part 3 Added verbiage to 3 3 5 Modified Figures 3 14 3 15 3 16 3 19 Modified Table 3 10 Part 5 Modified Figure 5 6 7 98 003 Restructured document and added a motherboard design Chapter 2 contains the Addin Card design This chapter combines revision 2 Chapters 1 2 3 and Appendix A Only re organizaiton the information is the same Chapter 2 adds the motherboard design ...

Page 9: ...1 Introduction ...

Page 10: ......

Page 11: ... graphics cards The basis of the design information is a reference ATX card design Schematics for the reference design are provided at the end of the chapter Chapter 3 3 Device AGP Motherboard Design This chapter provides design guidelines for developing a motherboard based on the Pentium II processor Intel 440BX AGPset and the Intel740 graphics accelerator The main focus of this chapter is the gu...

Page 12: ... com Bt829A Bt827A Bt825A VideoStreamII Decoders Oct 1996 Contact Rockwell Semiconductor Bt868 869 Flicker Free Video Encoder with UltrascaleTM Technology Contact Rockwell Semiconductor VMI 1 4 Interface Specification Contact SGS Thompson Microelectronics PC 98 Contact www microsoft com hwdev PC SGRAM Specification See Appendix B SO DIMM Module Specification See Appendix B Intel740 Graphics Accele...

Page 13: ...2 Intel740 Graphics Accelerator Addin Card Design ...

Page 14: ......

Page 15: ...his document contains the following features ATX Form Factor Memory 100 MHz SDRAM or SGRAM SO DIMM Memory Upgrade Socket 2 4 MB Solder Down Option BIOS Support for Flash or ROM Capable of Supporting up to 256KB Monitor Hardware Support for DDC 2B Video Capture Bi Directional VMI Video Port for DVD Hardware CCIR 601 8 16 bit Video Capture Port NTSC PAL and SECAM Inputs Accepted Intercast Capable Vi...

Page 16: ...z An SDRAM interface supports SGRAM and SDRAM to be used for different memory densities VMI Interface A bi directional VMI like port is incorporated into the Intel740 graphics accelerator providing a mechanism for affordable DVD Video capture is also supported using the video port pins TV Out Interface Intel has worked with Rockwell Brooktree to design an interface capable of supporting a high qua...

Page 17: ...turing data is through the use of the VMI protocol This interface is documented in the VMI 1 4 Interface Specification Flicker Filter Output The output of the Bt869 is a very high quality flicker filtered output This is due to a 5 tap internal filter Output can be displayed in interlaced non interlaced PAL or NTSC formats Macrovision7 output is also supported in the Bt869 component The Bt869 is ca...

Page 18: ...required between the VCC3 and VDDQ3 planes Stitching two isolated planes together with capacitors allows a current return path for high frequency signals which pass over split power planes This helps to eliminate EMI The six 0 1 µF capacitors coupling VCC3 to VDDQ3 should be spaced evenly if possible Note the VDDQ3 plane is only near the AGP connector An example of stitching is shown in Figure 2 2...

Page 19: ...bling a 4 layer design Figure 2 3 shows the four signal quadrants of the Intel740 graphics accelerator Component placement should be done with this general flow in mind This will simplify routing and minimize the number of signals which must cross The individual signals within the respective groups have also been optimized to be routed using only 2 PCB layers A complete list of signals and ball as...

Page 20: ... have an SO DIMM connector what video components to place on the board and which video connectors to have on the bracket will have to be evaluated by the board designer 2 2 2 Board Description Even with the following recommendations it is important to simulate your design A 4 layer stack up arrangement is recommended The stack up of the board is shown in Figure 2 5 The impedance of all the signal ...

Page 21: ...primary side are to be encroached with solder mask and anti pad unless board dryness has been guaranteed To minimize solder wicking with the BGA the component side solder mask should be applied prior to tinning the copper There should be no surface mount over bare copper S M O B C The solder mask must cover the trace between the via and pad The board impedance Z should be between 50 and 80 ohms 65...

Page 22: ...ected to a MBGA land or PTH via in the MBGA land grid array should be teardropped The teardrop should leave the trace at a 45 angle and intersect the via tangentially see Figure 2 7 The minimum distance between the gold finger edge of the card and the center of the first row of MBGA lands should be 525 mils and 480 mils from the end of the start of the bevel All BGA ground vias should use 16 mil d...

Page 23: ...GND plane as well as to the air on the solder side 2 2 3 3 Power Connections The VCC2 plane should be as wide as practical for high current carrying capacity Because of the interspersing of VCC2 and VCC3 pins on the Intel740 graphics accelerator a polygon will be needed on one of the signal layers to extend the VCC3 plane to the isolated VCC3 pins Figure 2 9 The VCC2 polygon is a separate plane on...

Page 24: ...erneath the component then decoupling is recommended at the corners of the Intel740 graphics accelerator package At least a 0 1 µF and 0 01 µF are recommended for each corner By placing the capacitors in this location all of the traces can break out from the BGA package on all four sides Figure 2 9 Suggested VCC Planes for the Intel740 Graphics Accelerator VCC2 VCC3 VCC2 on VCC Layer VCC3 on Secon...

Page 25: ...should have a spacing of 1 4 to other signals Using this extra spacing between these specific signals will help to keep crosstalk to a minimum 2 2 4 Voltage Regulator The physical tab used as a built in heatsink on the MOSFET package is the drain pin and will need a tab shaped pad to solder to Note The resistor capacitor network between the COMP pin pin 5 and the GND pin pin 3 of the LT1575 should...

Page 26: ...e parts include the 0 1µF and 0 01µF bypass capacitors the 10µF capacitors the 75 ohm terminating resistors and the crystal oscillator circuitry Note There must be NO digital signals routed under or above the analog power and ground planes AVCC and AGND The filter circuits on the four video input signals TUNER SV_LUM SV_CHR CV_IN need to be located near the 50 pin connector Note that other designs...

Page 27: ...ignals should be avoided Wherever analog signals run in parallel separated by less than 15 mils for longer than 250 mils run a ground line between the video input traces of approximately 12 mils width 2 2 6 4 AGP Layout and Routing Guidelines This section describes the group of signals that runs between the Intel740 graphics accelerator AGP Interface and the AGP edge connector For the definition o...

Page 28: ...mmercially available SO DIMMs and components Two SRAS lines permit two 64 bit wide rows of SDRAM All write operations must be one Quadword QWord The Intel740 graphics accelerator supports memory up to 100 MHz Rules for populating a Intel740 graphics accelerator Memory Memory can be populated using either an SO DIMM or components SDRAM and SGRAM components and or SO DIMMs can be mixed The DRAM Timi...

Page 29: ...gure 2 15 Signal Intel740 to SO DIMM SO DIMM to SGRAM Stub SGRAM Stub Min Max Min Max Min Max WEA SRASA SCASA CSA1 CSB0 n a 4 0 n a n a WEB SRASB SCASB CSA0 n a 4 0 0 25 0 9 0 25 0 6 Intel740 4 0 SGRAM SGRAM 0 25 0 9 0 25 0 6 SO DIMM 0 25 0 6 Intel740 Chip Intel740 3 0 SGRAM 0 9 SO DIMM 0 4 SGRAM 0 4 Intel740 Chip Figure 2 14 Layout Dimensions WEA SRASA SCASA CSA1 CSB0 Intel740 2 0 4 00 SO DIMM In...

Page 30: ...to Resistor Resistor to SO DIMM SO DIMM to SGRAM Stub SGRAM Stub Min Max TCLK0 0 6 2 4 0 25 n a n a n a TCLK1 0 6 2 4 0 25 1 0 0 4 0 6 Figure 2 16 Memory Layout Dimensions TCLK0 Figure 2 17 Memory Layout Dimensions TCLK1 Intel740 2 0 4 0 SGRAM SGRAM 0 25 0 6 0 25 0 6 0 25 0 9 Intel740 Chip Intel740 SO DIMM Connector 0Ω 2 4 0 25 0 6 Intel740 Chip Intel740 SO DIMM Connector 0Ω 2 4 0 25 0 6 Intel740 ...

Page 31: ...S signal Configuration 1 In this configuration the minimum amount of memory 2MB is supported Note that the same copy of all control signals goes to each component Signal Intel740 to Resistor OCLK to Resistor 2 75 0 25 RCLK0 RCLK1 3 0 0 25 Figure 2 18 Memory Layout Dimensions RCLK and OCLK to RCLK Intel740 33Ω 33Ω 2 75 0 25 OCLK RCLK0 RCLK1 3 0 0 25 3 0 0 25 Intel740 Chip Figure 2 19 2 4 MB Local M...

Page 32: ...ed Note that both rows of memory receive different copies of each control signal for loading reasons Figure 2 20 4 8 MB Local Memory Connection 64 bit data path Intel740 MD 63 0 CSx A B DQM 3 0 DQM 7 4 RCLKx OCLK MA 11 0 WEA SRASA SCASA TCLKA WEA SRASA SCASA TCLKA 256K 512K X 32 CS0A CS0A MD 31 0 MD 63 32 WEB SRASB SCASB TCLKB WEB SRASB SCASB TCLKB CS1A CS1A MD 31 0 MD 63 32 256K 512K X 32 256K 51...

Page 33: ...orted in this configuration Note that each copied signal is sent to only two components Figure 2 21 8 MB Local Memory Connection 64 bit data path Intel740 MD 63 0 CSx A B RCLKx OCLK MA 11 0 WEA SRASA SCASA TCLKA WEB SRASB SCASB TCLKB 1M X 16 CS0A CS0B MD 15 0 MD 31 16 WEA SRASA SCASA TCLKA WEB SRASB SCASB TCLKB CS0A CS0B MD 47 32 MD 63 48 1M X 16 1M X 16 1M X 16 DQM 1 0 DQM 7 6 DQM 3 2 DQM 5 4 Int...

Page 34: ...component and outputs from the Bt869 component 2 2 7 UL and FCC Considerations Certain precautions should be taken in the design of the of a graphics card to ensure passing safety and EMI tests These precautions are listed below When a signal can be hot plugged clamping diodes should be used to limit voltage spikes When a voltage leaves the card a fuse should be placed in the path to protect from ...

Page 35: ... down These pins contain a strapping option for subsystem ID In this case the reference design has an ID of 0100h Bits that should be a 1 may be pulled up using a 2K pull up resistor If the graphics design will not have video the only concern is pulling the bus up to the correct value for the subsystem ID The video control signals may be left unconnected The BIOS interface multiplexes the BIOS ven...

Page 36: ... bottom of the page Bt869 Schematic Page 7 The Bt869 power supply is generated from the VCC3 supply Decoupling for this supply is shown at the top of the page The component contains a 24 bit data port The Intel740 graphics accelerator connects only to 12 of these bits The functionality of this interface is described in the Intel740 Graphics Accelerator Datasheet The slave input is tied to ground t...

Page 37: ...ls Note that the primary CS0 connection is tied to the Intel740 graphics accelerator CSA1 signal The CSB0 signal is connected to CS1 on the connector The reference design has the first row of memory down on the graphics card The second row of memory is assumed to be placed in the SO DIMM connector Note It is important not to have the memory on the graphics card and memory on the SO DIMM connector ...

Page 38: ...M X 16 Pinout Compatibility A8 AP A9 BS A10 A7 A0 A9 AP A10 BS A8 A7 A0 Pin 51 Pin 29 Pin 30 Intel740 512Kx32 SGRAM Jedec Standard A8 AP A9 BS A10 A7 A0 A8 AP A9 BS NC A7 A0 Pin 51 Pin 29 Pin 30 Intel740 256Kx32 SGRAM Jedec Standard Intel740 Chip Intel740 Chip Intel740 Chip A11 BS A10 AP A9 A8 A1 A0 A11 A10 A9 A8 A1 A0 1M X 16 SDRAM ...

Page 39: ...IOS used in this design is a PLCC socket for early debug capabilities To use less board space a TSOP package may be the preferred component Since the selected part is a 5 volt part the data lines are isolated from the Intel740 graphics accelerator by a level shifter Note The Intel740 graphics accelerator does not require a fan for AGP compliant systems These design features have been added for eas...

Page 40: ...Addin Card Design 2 26 Intel740 Graphics Accelerator Design Guide ...

Page 41: ...RCHANTABILITY FITNESS FOR ANY PARTICULAR PURPOSE OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL SPECIFICATION OR SAMPLE NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PRPERTY RIGHTS IS GRANED HEREIN INTEL DISCLAIMS ALL LIABILITY INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS RELATING TO USE OF INFORMATION IN THIS SPECIFICATION INTEL DOES NOT WARRANT O...

Page 42: ...TOR p 9 VGA DDC CONNECTOR p 10 TV TUNER CONNECTOR p 14 VIDEO ENCODER INTEL740 TM Graphics Accelerator p 3 4 p 7 p 13 GRAPHICS MEMORY FLASH p 15 BIOS CNTL ADDR DATA ADDR DATAA ADDR DATA CNTL AGP SIDEBAND Intel740 TM Graphics Accelerator Reference Card 2 1 Block Diagram B 2 16 Thursday April 09 1998 Title Size Document Number Rev Date Sheet of ...

Page 43: ...CCP D13 VCCP AB10 VCCP D14 VDDQ J05 VCCP E15 VCCP AB12 VCCP E17 VCCP E19 VCCP AC13 VDDQ L05 VCCP AC14 VCCP AB15 VDDQ N05 VCCP AB17 NC H26 VCCP AB19 VDDQ P05 VCCP AC21 VCCP Y22 VDDQ T05 VCCP V22 VCCP T22 VDDQ V05 VCCP P22 VCCP N22 VDDQ Y05 VCCP L22 VCCP J22 VCCP G22 NC H25 VSS A04 VSS A05 VSS A22 VSS A23 VSS A24 VSS A26 VSS B01 VSS B02 VSS B04 VSS A25 VSS B03 ST0 G01 VMIHA0 A16 ST1 H04 ROMD0 B07 ST...

Page 44: ...S AC22 VSS AC23 VSS AC24 VSS AC25 VSS AC26 VSS AD01 VSS AD02 VSS AD03 VSS AD04 VSS AD05 VSS AD22 VSS AD23 VSS AD24 VSS AD25 VSS AD26 VSS AE01 VSS AE02 VSS AE03 VSS AE04 VSS AE05 VSS AE22 MD40 U22 MD31 AE15 GPIO0 K23 RSVD AA24 MD32 W22 MD41 V25 GPIO1 K24 MD33 Y25 MD42 U23 GPIO4 C14 MD34 W23 MD43 V26 RSVD AE08 GPIO5 B14 MD35 Y26 MD44 U24 DQM0 AD10 MD36 W24 GPIO6 A14 MD45 U25 RSVD AE14 MD46 T23 MD39 ...

Page 45: ...TUFF EMPTY STUFF EMPTY 3 3V 2 7V EMPTY STUFF STUFF EMPTY 2 7V 2 7V STUFF EMPTY EMPTY STUFF 3 3V 3 3V EMPTY STUFF EMPTY STUFF 2 7V 3 3V DEFAULT THE DEFAULT POWER CONFIGURATION IS NOT REPRESENTED HERE Intel740 TM Graphics Accelerator Reference Card 2 1 Voltage Regulator A 5 16 Thursday April 09 1998 Title Size Document Number Rev Date Sheet of L_GATE COMP1 FB1575 R_GATE M_COMP1 VCC_REGULATED VCC3 12...

Page 46: ...C45 01UF C100 1UF C101 01UF C13 10UF C14 10UF C32 01UF C29 1UF C4 01UF C3 1UF C28 1UF C49 1UF L6 2 7UH BT829B U4 GND 75 GND 71 GND 66 GND 61 GND 58 GND 56 GND 54 GND 47 GND 42 NC 68 NC 101 NC 51 NC 46 NC 63 NC 70 NC 69 GND 11 GND 21 GND 31 GND 33 GND 39 GND 77 GND 81 GND 90 GND 93 GND 95 GND 100 TRST 35 TDO 32 TDI 37 TMS 36 TCK 34 AVCC 40 AVCC 48 AVCC 44 VD0 29 AVCC 60 AVCC 65 VD1 28 AVCC 72 VD2 2...

Page 47: ...7 1UF C69 1UF C56 1UF C68 01UF C96 10UF C93 1UF C94 01UF C71 1UF FB3 FB 1 2 BT868 869 U8 1P P 11 16 P 12 17 P 13 18 P 14 23 P 15 24 P 16 25 P 17 26 P 18 27 P 19 28 P 20 29 P 21 32 P 22 33 P 23 34 VSS 4 AGND1 1 VSS 21 DACA 68 VSS 39 AGND2 79 P 0 5 AGND_DAC1 65 DACB 70 AGND_DAC2 74 P 1 6 DACC 72 P 2 7 P 3 8 P 4 9 P 5 10 P 6 11 P 7 12 P 8 13 P 9 14 P 10 15 VAA_PLL 59 VAA 80 VAA_DACA 69 VAA_DACC 73 VA...

Page 48: ...14 TP_07Z15 TP_07Y15 TP_07Y20 TP_07Y19 TP_07Y18 5VVP8 5VVP9 5VVP11 5VVP12 5VVP13 5VVP14 TP_0724 TP_0726 TP_0723 L5VVCLK L5VHREF 5VVP10 5VVP15 12V VCC VCC3 2X20RCPT J7 2X20RCPT USRDEF Y17 GND Y2 USRDEF Z17 3 3V Y16 USRDEF Z18 GND Y11 5V Y9 GND Z3 3 3V Z13 GND Z10 HD0 Y1 5V Z5 HA0 Y7 5V Z16 HD1 Z2 HA1 Z8 HD2 Y3 HA2 Y8 HD3 Z4 HA3 Z9 HD4 Y4 HD5 Y5 HD6 Z6 HD7 Y6 INSERT Z19 RESET Y10 WR Y12 READY Y13 IN...

Page 49: ... B63 AD4 A62 AD5 B62 AD6 A60 AD7 B60 AD8 B57 AD9 A56 AD10 B56 AD11 A54 AD12 B54 AD13 A53 AD14 B53 AD15 A51 AD16 A39 AD17 B38 AD18 A38 AD19 B36 AD20 A36 AD21 B35 AD22 A35 AD23 B33 AD24 A30 AD25 B30 AD26 A29 AD27 B29 AD28 A27 AD29 B27 AD30 A26 AD31 B26 OVRCNT B1 GND A5 PME A48 SBA0 B15 RSVD A2 GND B5 RSVD B14 SBA1 A15 RSVD A14 GND A13 RSVD A42 SBA2 B17 RSVD B42 GND B13 RSVD A44 SBA3 A17 RSVD B44 GND...

Page 50: ...f L_RED L_GREEN L_BLUE MON2PU FUSE_5 MON0PU VGA_HSYNC VGA_VSYNC 5VDDCCL VCC VCC VCC VCC3 VCC3 C67 22PF C66 22PF C47 22PF C46 22PF C42 22PF C41 22PF FB4 FB 1 2 FB2 FB 1 2 FB1 FB 1 2 R2 1K R34 75 R28 75 R25 75 t RT1 THERMISTOR R1 1K R20 0 R21 0 CR2 BAV99 1 2 3 CR4 BAV99 1 2 3 CR5 BAV99 1 2 3 CR3 BAV99 1 2 3 CR1 BAV99 1 2 3 J2 VGA CONN 6 5 15 10 4 14 9 3 13 8 2 12 7 1 11 RED 4 GREEN 4 BLUE 4 5VDDCDA ...

Page 51: ... R14 10K R15 10K R29 10K R13 2 2K QS3861 U2 QS3861 QSV 24 GND 12 B0 22 A8 10 B1 21 A0 2 B2 20 A9 11 B3 19 A1 3 B4 18 A2 4 B5 17 A3 5 B6 16 A4 6 B7 15 A5 7 B8 14 A6 8 B9 13 A7 9 BE 23 NC 1 QS3861 U5 QS3861 QSV 24 GND 12 B0 22 A8 10 B1 21 A0 2 B2 20 A9 11 B3 19 A1 3 B4 18 A2 4 B5 17 A3 5 B6 16 A4 6 B7 15 A5 7 B8 14 A6 8 B9 13 A7 9 BE 23 NC 1 QS3861 U3 QS3861 QSV 24 GND 12 B0 22 A8 10 B1 21 A0 2 B2 2...

Page 52: ...VCC3 113 VCC3 27 VCC3 114 VCC3 28 VCC3 129 VCC3 47 VCC3 130 VCC3 48 VCC3 143 VCC3 63 VCC3 144 VCC3 64 VCC3 75 VCC3 76 RSVD 77 DQMB0 118 RSVD 78 DQMB1 117 DQMB2 116 DQMB3 115 DQMB4 26 DQMB5 25 DQMB6 24 DQMB7 23 A0 92 A1 91 A2 90 A3 89 A4 88 A5 87 A6 84 A7 83 A8 82 A9 81 RSVD A10 80 RSVD A11 79 DQ0 138 DQ1 137 DQ2 136 DQ3 135 DQ4 134 DQ5 133 DQ6 132 DQ7 131 DQ8 128 DQ9 127 DQ10 126 DQ11 125 DQ12 124...

Page 53: ...BA 29 DQM0 23 DQM1 56 DQM2 24 DQM3 57 DQ0 97 DQ1 98 DQ2 100 DQ3 1 DQ4 3 DQ5 4 DQ6 6 DQ7 7 DQ8 60 DQ9 61 DQ10 63 DQ11 64 DQ12 68 DQ13 69 DQ14 71 DQ15 72 DQ16 9 DQ17 10 DQ18 12 DQ19 13 DQ20 17 DQ21 18 DQ22 20 DQ23 21 DQ24 74 DQ25 75 DQ26 77 DQ27 78 DQ28 80 DQ29 81 DQ30 83 DQ31 84 CLK 55 VDDQ 59 VREF MCH 58 NC DRDY 95 CKE 54 CS 28 RAS 27 CAS 26 WE 25 DSF 53 VCC3 96 NC 101 SGRAM 512Kx32 U6 SGRAM 512Kx...

Page 54: ...et of CONX_20 SVINY CONX_24 RCA_IN SVINC TVTUNER12V CONX_47 TVTUNERIN TP_1429 TP_1428 TP_1427 TP_1426 TP_1401 TP_1402 TP_1403 TP_1404 TP_1405 12V C31 330PF L5 3 3UH L2 3 3UH L8 1 8UH C15 330PF L9 1 8UH C90 330PF C85 220PF C103 22PF C102 330PF C18 330PF C37 330PF C104 220PF C84 22PF C91 22PF L7 1 8UH C30 330PF L1 3 3UH t RT2 THERMISTOR L4 3 3UH C19 330PF C20 330PF C92 220PF C83 330PF C26 330PF J5 5...

Page 55: ...ANPOWER ROMA9 ROMA6 5VROMD6 ROMA16 3VROMD0 3VROMD2 3VROMD4 3VROMD5 3VROMD7 3VROMD1 3VROMD3 3VROMD6 QSV 12V VCC VCC VCC VCC3 VCC3 VCC VCC J3 1X3HDR 1 2 3 C73 01UF R27 4 7K R33 0 R16 4 7K C72 1UF R23 0 C97 1UF C99 01UF R48 2K U1 2 74LVT125 4 5 6 C119 22UF Q1 MOSFET P QS3861 U13 QS3861 QSV 24 GND 12 B0 22 A8 10 B1 21 A0 2 B2 20 A9 11 B3 19 A1 3 B4 18 A2 4 B5 17 A3 5 B6 16 A4 6 B7 15 A5 7 B8 14 A6 8 B...

Page 56: ...SE ARE THE AC CAPS TO MUX INPUTS THIS REQUIRED A PACKAGE SIZE CHANGED FROM 0805 TO 1206 VCC CONNECTION TO PIN 59 OF BT829B P 5 DELETED WIRE LEFT OPEN AND RENAMED TP_0559 REMOVED NOTE NEAR PIN 59 OF BT829B P 5 WHICH STATED TIE TO ANALOG FENCE DELETED R13 R18 R19 FROM P 5 OF SCHEMATICS REPLACED C38 ON P 5 WITH A SHORT THE SIGNALS MUXOUT AND YIN WERE THUS REMOVED AND RENAMED AS ONE SIGNAL MUXOUT_YIN ...

Page 57: ...3 Intel740 Graphics Accelerator 3 Device AGP Motherboard Design ...

Page 58: ......

Page 59: ...m the system The desire for a 3 point AGP solution is to allow an upgrade path from the master device on the motherboard to a master device on an add in card This section contains references to sections already discussed in the reference card section of this design guide Since the focus of this section is only the 3 point AGP implementation with the Intel740 graphics accelerator many of the layout...

Page 60: ...also provides implementation issues associated with a 3 point AGP design and design recommendations which Intel feels will provide flexibility to cover a broader range of products within a market segment Section 3 2 3 Device AGP Motherboard Layout and Routing Guidelines This section provides detailed layout routing and placement guidelines for the AGP bus and local memory subsystem Design guidelin...

Page 61: ...emselves Since the current AGP specification has made no provision for a general method of disabling a master device this function must be defined for on an individual basis depending on the operating characteristics of each master device The graphics controller that is used as the down device on the motherboard must have a mechanism that disables the device in a manner acceptable to the implement...

Page 62: ...ignals GPO27 and GPO 28 from the PIIX4E are used in this design GPO28 in conjunction with ROMA16 and PCIRST are used to put the Intel740 chip in low power mode see Figure 3 2 The additional logic for driving WEB SCASB SRASB CS0B CS1B and TEST is illustrated in Figure 3 2 A hardware reset to the Intel740 chip takes the device out of the low power state Since the PCIRST signal is used to disable the...

Page 63: ...rement is set by the minimum reset time defined in the Accelerated Graphics Port Interface Specification Revision 1 0 GPO28 puts the device into low power mode and should be a minimum duration of the sum of the propagation delay for logic depicted in Figure 3 2 Figure 3 3 The Schematic Diagram for the WEB SCASB SRASB CS0B CS1B and TEST Table 3 2 Signal Duration of the GPO Signals from PIIX4 Signal...

Page 64: ...use both GPO27 and GPO28 should be driven high 1 The Intel740 graphics controller down on the motherboard enters the low power mode at system reset If an enabling event occurs the device enters the functional mode from the low power mode See Figure 3 5 The following are examples in which functional mode would be invoked Intel740 graphics accelerator as the primary and only graphics device Multimon...

Page 65: ...o verify proper operation of the AGP system Both the case where an add in card is present in the system and the case where the add in card is not in the system must be evaluated for a complete solution Depending on how the system is designed the bus will become balanced or unbalanced depending on the add in card being in or out of the system Specific design issues faced in implementing a logical p...

Page 66: ...t and the AGP target chipset must be within the 1ns limit called out in the AGP specification Since we had a driver skew of 0 25ns due to the clock drivers this meant that our propagation delays and settling times skews could not exceed 0 75 ns This means that for a single clock driver solution not only must each of the two clock trace segments be balanced in such a way that signal quality is acce...

Page 67: ...e a robust design Follow these guidelines as closely as possible Any deviations from the guidelines listed should be simulated to insure adequate margin is still maintained in the design Since the concentration of this section is mainly 3 Device AGP implementation refer to the Intel 440BX AGPset Design Guide for the remaining design guidelines It would be beneficial to have that design guide befor...

Page 68: ...fabrication costs down by enabling a 4 layer design Figure 3 7 shows the four signal quadrants of the Intel740 graphics accelerator Component placement should be done with this general flow in mind This will simplify routing and minimize the number of signals which must cross The individual signals within the respective groups have also been optimized to be routed using only 2 PCB layers A complet...

Page 69: ...r design the AGP compliant graphics device can be either on the motherboard device down option or on an AGP connector up option 4 The trace length limitation between critical connections will be addressed later in this document 5 Figure 3 8 is for reference only and the trade off between the number of PCI and ISA slots number of DIMM sockets and other motherboard peripherals need to be evaluated f...

Page 70: ...possible to use single ended termination if the trace lengths can be tightly controlled to a 1 5 minimum and 4 0 maximum The termination resistors on the GTL bus should be 56 ohms 5 The board impedance Z should be 65 ohms 15 FR 4 material should be used for the board fabrication The ground plane should not be split on the ground plane layer If a signal must be routed for a short distance on a powe...

Page 71: ...ameters These parameters include trace width and space impedance and variation and or dielectric thickness All of these parameters may have an effect on the solution space which could allow the bus to be routed Note that is has been shown that moving to a wider trace and space ratio has increased the segment length for the 3 load bus The length gained to enable routing the bus comes at the cost of...

Page 72: ...the plugin card provided to us were routed as microstrip The clock trace on the add in card shall be routed to achieve an interconnect delay of 0 6ns 0 1ns as determined from trace length and trace velocity 3 2 3 5 Motherboard Guideline Assumptions Data Signal and Strobe Requirements The motherboard needed to have an impedance range of 50Ω to 80Ω as recommended by the 82443BX design guide This ran...

Page 73: ...y Clock Line Matching Skew between each AGP master clock input and the AGP target chipset must be within the 1ns limit called out in the AGP specification The driver use on this design can have up to 0 25ns of skew from output to output This means that propagation delays and settling time skews cannot exceed 0 75 ns Thus for a single clock driver solution not only must each of the two clock trace ...

Page 74: ... is segment A to connector connector to segment B 3 2 3 7 Overall Solution Space Two solution spaces were found Selecting the appropriate solutions is dependent on the 82443BX placement relative to the AGP connector Solution 1 was implemented on this design Solution 1 Note that A B within a group must be matched by 0 5 Example Figure 3 11 3 Device Data Load Topology 82443BX Segment A Connector Seg...

Page 75: ... 3 13 3 Device Data Load Topology Solution 1 is Shown Figure 3 14 3 Device Strobe Load Topology Solution 1 is shown 82443BX Segment A Connector Segment B Intel740 Chip Segment D Segment C AGP Master Motherboard Add In Card 3 5 5 5 0 4 0 9 0 3 0 2 0 3 0 82443BX Segment A Connector Segment B Intel740 Chip Segment D Segment C AGP Master Motherboard Add In Card 3 5 5 5 0 4 0 9 0 3 0 2 0 3 0 Figure 3 1...

Page 76: ...ts Two SRAS lines permit two 64 bit wide rows of SDRAM All write operations must be one Quadword QWord The Intel740 graphics accelerator supports memory up to 100 MHz Rules for populating a Intel740 graphics accelerator Memory SDRAM and SGRAM components can be mixed The DRAM Timing register which provides the DRAM speed grade control for the entire memory array must be programmed to use the timing...

Page 77: ...MA 11 0 25 4 9 0 25 0 6 MD 63 0 DQM 7 0 25 3 9 0 25 0 4 Figure 3 16 Layout Dimensions MA 11 0 Figure 3 17 Layout Dimensions MD 63 0 DQM 7 0 Table 3 12 Memory Layout Restrictions See Table 3 16 and Table 3 17 Signal Intel740 to SGRAM Stub SGRAM Stub Min Max Min Max WEA SRASA SCASA CSA0 2 25 4 9 0 25 0 6 Intel740 Chip 0 25 4 9 SGRAM SGRAM 0 25 0 6 0 25 0 6 Intel740 Chip 0 25 3 9 SGRAM SGRAM 0 25 0 6...

Page 78: ...CLK should be 3 03 OCLOCK to Resistor 2 Figure 3 18 Layout Dimensions WEA SRASA SCASA CSA0 Table 3 13 Memory Layout Restrictions See Figure 3 19 Signal Intel740 to Resistor Resistor to SGRAM Stub SGRAM Stub Min Max TCLK1 0 6 3 4 0 25 0 4 0 6 Figure 3 19 Memory Layout Dimensions TCLK1 Signal Intel740 to Resistor OCLK to Resistor 1 0 0 25 RCLK0 RCLK1 3 0 0 25 Intel740 Chip 2 25 4 9 SGRAM SGRAM 0 25 ...

Page 79: ...ion 1 In this configuration the minimum amount of memory 2MB is supported Note that the same copy of all control signals goes to each component Figure 3 20 Memory Layout Dimensions RCLK and OCLK to RCLK Intel740 Chip 1 0 0 25 33 OCLK RCLK0 RCLK1 33 3 0 0 25 3 0 0 25 Figure 3 21 2 4 MB Local Memory Connection 64 bit data path Intel740 MD 63 0 CSx A B DQM 3 0 DQM 7 4 RCLKx OCLK MA 11 0 WEA SRASA SCA...

Page 80: ...he new clock synthesizer component the CK100 plus recommended decoupling The clock synthesizer components must meet all of the system bus PCI and other system clock requirements Several vendors offer components that can be used in this design This page also shows the In Target Probe ITP Connector The ITP connector is recommended in order to use the In Target Probe tool available from Intel and oth...

Page 81: ...47 on each DIMM socket should be pulled high to enable registered DIMMs PIIX4E Component P 12 This page shows the PIIX4E component The PIIX4E component connects to the PCI bus dual IDE connectors and the ISA bus This reference design supports a subset of the power management features of the PIIX4E PIIX4E Component P 13 This page shows the PIIX4E component Interrupts USB DMA power management X Bus ...

Page 82: ...linear regulator device such as the LT1585A 1 5 supplying the entire 5 0 amps can be used if both ends of the GTL bus traces are near each other For dual processors two LT1587 1 5s 3A are recommended Power Connectors Front Panel Jumpers P 26 This page shows the system ATX power connector hardware reset logic and standard chassis connectors for the hard disk power LEDs and speaker output New to thi...

Page 83: ...lly the input pins are pulled down These pins contain a strapping option for subsystem ID In this case the reference design has an ID of 0100h Bits that should be a 1 may be pulled up using a 2K pull up resistor Since this graphics design will not have video the only concern is pulling the bus up to the correct value for the subsystem ID The video control signals may be left unconnected The BIOS i...

Page 84: ... 740 chip is disabled and will not initiate or respond to cycles on the AGP bus Figure 3 22 512Kx32 and 256Kx32 Pinout Compatibility Figure 3 23 1M X 16 Pinout Compatibility A8 AP A9 BS A10 A7 A0 A9 AP A10 BS A8 A7 A0 Pin 51 Pin 29 Pin 30 Intel740 512Kx32 SGRAM Jedec Standard A8 AP A9 BS A10 A7 A0 A8 AP A9 BS NC A7 A0 Pin 51 Pin 29 Pin 30 Intel740 256Kx32 SGRAM Jedec Standard Intel740 Chip Intel74...

Page 85: ...to 2 7 Volts The regulator used in the reference design does not need any heatsink for the FET As shown the FET will be dissipating slightly over 1 watt If a different voltage regulator solution will be used calculations will be needed to determine the need for a heatsink Core decoupling is shown at the bottom of the page and should be placed close to the Intel740 graphics accelerator Revision His...

Page 86: ...3 Device AGP MotherBoard Design 3 28 Intel740 Graphics Accelerator Design Guide ...

Page 87: ...ties including Philips Electronics N V and North American Philips Corporation No license express or implied by estoppel or otherwise to any intellectual property rights is granted herein 9 10 11 2 1 25 PARALLEL 3 4 SLOT1CONNECTOR GTL TERMINATION COVERSHEET Intel disclaims all liability including liability for infringement of any proprietary rights relating to use of information in this specificati...

Page 88: ...S PROCESSOR PG 27 2 PCI IDE PG 12 13 ADD DATA PG 15 SER CNTL VGA FLOPPY MOUSE PG 14 CNTL CNT L 82371EB CK100 PIIX4E MAX1617 ME PG 5 DECOUPLINGCAPACITORS CONN PG 33 ADDR ULTRA I O SLOT 1 492 BGA CNTL CNTL CONN PG 3 FLASH PG 28 29 DATA PG 20 PG 6 8 USB CKBF PG 6 DATA PARA ADDR ISA PCI RESISTORS INTEL SECRET ADD LM79 PG 23 PG 19 ADDR CNT L ITP CON ISA CONN PRIMARY IDE GRAPHICS X BUS CONTROL DATA PG 1...

Page 89: ...C_CORE 100 66 VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE RESERVED LINT 1 PICCLK BP 2 RESERVED PICD 1 PRDY BPM 1 DEP 2 DEP 4 DEP 7 D 62 D 58 D 63 D 56 D 50 D 54 D 59 D 48 D 52 EMI D 41 D 47 D 44 D 36 D 40 D 34 D 38 D 32 D 28 D 29 D 26 D 25 D 22 D 19 D 18 EMI D 20 D 17 D 15 D 12 D 7 D 6 D 4 D 2 D 0 U16A SLOT1_0 8 B01 A01 B02 A02 B03 B04 A03 B05...

Page 90: ... 4 BNR BPRI TRDY DEFER REQ 2 REQ 3 HITM DBSY RS 1 RESERVED ADS AP 0 VID 2 VID 1 VID 4 VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE RESET BREQ1 FRCERR A 35 A 32 A 29 EMI A 26 A 24 A 28 A 20 A 21 A 25 A 15 A 17 A 11 A 12 A 8 A 7 A 3 A 6 EMI SLOTOCC REQ 0 REQ 1 REQ 4 LOCK DRDY RS 0 VCC_5 VCC_3 VCC_3 VCC_3 HIT RS 2 RESERVED RP RSP AP 1 AERR VID 3 VID 0 U16B SLOT1_0 8 B74 A74 B75 A75 B76 B77 A...

Page 91: ...4 40 25 27 5 9 28 42 43 15 3 26 19 21 31 41 30 46 29 48 33 7 6 12 18 38 32 24 20 37 39 36 35 8 10 11 13 14 16 17 23 22 45 44 1 2 47 34 XTALIN CPUCLK0 SEL_100 66 SEL0 XTALOUT VDDPCI0 RESV RESV VSSAPIC VDDPCI1 VSSREF SEL1 VDDCORE0 VDD48MHZ PCI_STP VDDCPU0 CPU_STP VDDAPIC PWRDWN VDDQREF VDDCORE1 PCICLK_F VSSPCI0 VSSPCI1 VSSPCI2 VSSCPU0 VSSCORE1 VSS48MHZ VSSCORE0 VDDCPU1 CPUCLK1 CPUCLK2 CPUCLK3 PCICLK...

Page 92: ... C25 AD25 J23 AB22 A24 D24 C23 K24 B24 C24 K25 A23 E22 D23 J25 N23 B26 AE22 AE23 P22 A1 A14 A26 C5 C9 C18 C22 E3 E12 E15 E24 F6 F8 F19 F21 H6 H21 J3 J24 V21 Y21 F7 F9 F18 F20 G6 G21 J6 J21 AA7 AA9 AA18 AA20 DQMA0 CRESET WE_B SRAS_A SRAS_B ADS WE_A CSA0 MAB1 MAB0 MAA2 SCAS_A HA3 SCAS_B MAB5 MAA3 MAB4 MAB2 MAA4 PCIRST CPURST MAA5 MAB3 TESTIN HA4 MAA6 HA5 MAA0 BNR MAB6 MAA7 MAA1 HA6 BPRI MAB7 HA7 MAB...

Page 93: ... R11 R13 R14 R16 R22 V3 V24 W6 W21 P5 N5 N11 N16 P11 P16 R12 R15 T11 T13 T14 M15 M12 L16 L14 L13 L11 T16 VDD PREQ0 IOREQ VDD FRAME VDD AGPREFV VDD C BE0 VDD GADSTB B PREQ1 GADSTB A AD0 DEVSEL ST2 PREQ2 ST0 SB STB C BE1 IRDY PREQ3 PIPE ST1 PGNT0 IOGNT GFRAME TRDY SBA0 C BE2 AD1 PGNT1 GC BE0 AD2 STOP PREQ4 C BE3 SBA1 AD3 PGNT2 PLOCK AD4 PAR AD5 GDEVSEL AD6 SBA2 AD7 GAD0 AD8 PGNT3 AD9 SBA3 AD10 SERR ...

Page 94: ...B15 C19 E21 A15 D14 B19 AC6 D15 A18 A22 B13 C14 E14 A19 D13 AA10 D21 B18 A13 D12 C17 B12 B14 C21 E17 U23 C13 E13 D17 A21 D11 A12 C20 B11 AA23 A11 B21 B7 C12 E20 C8 B10 AF6 A20 A10 A9 E19 A7 AA26 E11 B20 D9 C11 AC10 C10 B8 AF11 A8 B9 AD7 AD12 T22 AA25 AE7 Y22 AF4 AC8 T23 AD8 AF10 AF8 T26 AE8 AF9 R24 AD10 AD11 AE10 R25 AB11 AE4 AC11 P23 Y23 Y24 Y26 N25 W22 AF5 V22 AC5 V23 Y25 V25 AE5 U22 U25 AB6 U26...

Page 95: ...4 115 31 48 42 125 79 163 80 164 81 61 63 147 50 51 52 53 112 113 130 131 45 129 128 132 44 43 54 64 68 78 127 138 148 152 162 62 146 49 59 73 84 143 157 168 133 33 117 34 118 35 119 36 120 37 121 38 122 39 123 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 126 ...

Page 96: ... 52 53 112 113 130 131 45 129 128 132 44 43 54 64 68 78 127 138 148 152 162 62 146 49 59 73 84 143 157 168 133 33 117 34 118 35 119 36 120 37 121 38 122 39 123 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 55 56 57 58 60 65 66 67 69 70 71 72 74 75 76 77 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 126 21 134 135 136 137 165 166 167 82 83 145 VCC VCC VC...

Page 97: ... 8 9 10 11 22 24 25 105 106 108 109 28 29 46 47 41 90 102 124 1 12 18 23 32 85 96 107 116 110 27 111 30 114 115 31 48 42 125 79 163 80 164 81 61 63 147 50 51 52 53 112 113 130 131 45 129 128 132 44 43 54 64 68 78 127 138 148 152 162 62 146 49 59 73 84 143 157 168 133 33 117 34 118 35 119 36 120 37 121 38 122 39 123 13 14 15 16 17 19 20 86 87 88 89 91 92 93 94 95 97 98 99 100 101 103 104 55 56 57 5...

Page 98: ... B12 A12 A6 D5 C5 A17 F18 A16 F17 F16 E10 A11 G20 B11 C11 C16 B16 D16 PCS1 SCS1 PCS3 SCS3 SDD0 PDDACK SDD1 SDA0 SDD2 PDD0 SDD3 SDA1 SDD4 PDA0 SDD5 SDA2 SDD6 PDD1 SDD7 PDD2 SDD8 PDA1 SDD9 PDD3 SDD10 PDA2 SDD11 PDD4 SDD12 PDD5 SDD13 PDD6 SDD14 AD0 SDD15 PDD7 PDD8 AEN BALE AD1 IOCHK PDD9 IOCHRDY IOCS16 LA17 LA18 IOR LA19 PDD10 LA20 IOW LA21 AD2 LA22 SA19 SA0 LA23 SA1 PDD11 SA2 MEMCS16 SA3 PDD12 SA4 M...

Page 99: ...PI9 BATLOW USBP1 DACK2 RSMRST USBP0 DREQ0 PWRBT DREQ1 GPI10 LID DREQ2 SMBDATA DREQ3 SMBCLK DREQ5 SUSCLK DREQ6 REQA GPI2 REQB GPI3 REQC GPI4 GNTA GPO9 GNTB GPO10 GNTC GPO11 TC MCCS APICACK GPO12 GPI14 APICCS GPO13 GPI15 APICREQ GPI5 GPI16 OC0 RCIN OC1 GPI17 IRQ0 GPO14 GPI18 IRQ1 VREF GPI19 GPI20 GPI1 IRQ3 GPI21 IRQ4 GPI12 RI A GPI11 SMBALERT IRQ5 IRQ6 IRQ7 N C GPO0 IRQ8 GPI6 N C IRQ9 N C N C GPO27 ...

Page 100: ...WOP IDE_A0 IDE_A1 IDE_A2 SA12 CS SA13 HDCS2 SA14 HDCS3 SA15 IDE2_IRQ KCLK KDAT MSCLK MSDAT RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 ROMCS ROMDIR 14CLK01 14CLK02 14CLK03 16CLK 24CLK INDEX DIR STEP WDATA WGATE TRK0 WPT RDATA SIDE1 DSKCHG MTR0 MTR1 DRVSEL0 DRVSEL1 DRVDEN0 DRVDEN1 MEDID0 MEDID1 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 DRQ0 DRQ1 DRQ2 DRQ3 DACK0 DACK1 DACK2 DACK3 SLIN INIT...

Page 101: ... B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 12V OVRCNT SPARE RESERVED 5V USB 5V GND USB INTA RST GND GNT VCC3 3 INTB ST1 RESERVED CLK PIPE GND REQ SPARE SBA1 VCC3 3 VCC3 3 SBA3 ST0 RESERVED AD30 ST2 AD28 VCC3 3 RBF AD26 AD24 GND GND RESERVED SPARE GC BE3 Vddq3 3 SBA0 AD22 AD20 VCC3 3 GND AD18 SBA2 AD16 Vddq3 3 SB_STB FRAME SPARE GND ...

Page 102: ...V C BE 3 GND AD 23 GND RSV AD 21 AD 19 RESET 3 3V AD 17 5V C BE 2 GND GNT IRDY 3 3V GND DEVSEL GND PME LOCK PERR AD 30 3 3V AD 27 SERR 3 3V 3 3V C BE 1 AD 28 AD 14 GND AD 26 AD 12 AD 10 GND GND AD 7 AD 24 3 3V AD 5 IDSEL AD 3 GND 3 3V AD 1 AD 8 5V AD 22 ACK64 5V AD 20 5V GND AD 18 AD 16 3 3V FRAME GND TRDY GND STOP 3 3V SDONE SBO GND PAR AD 15 3 3V AD 13 AD 11 GND AD 09 3 3V AD 06 AD 04 GND AD 02 ...

Page 103: ...49 B53 A25 B54 B55 A26 B56 B57 A27 B58 B52 B59 A28 B60 B61 A29 B62 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A53 A54 A55 A56 A57 A52 A58 A60 A61 A59 A62 INTB 12V INTD TRST TCK GND 12V TDO 5V TMS 5V TDI PRSNT1 5V RSV PRSNT2 INTA GND GND INTC RSV GND 5V CLK GND RSV REQ 5V 5V AD 31 AD 29 RSV GND AD 25 GND 3 3V C BE 3 GND AD 23 GND RSV AD 21 AD 19 RESET 3 3V AD 17...

Page 104: ...2 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD3 12 14 29 AEN 12 14 IRQ11 13 14 29 SA18 12 21 29 IRQ3 13 14 29 LA20 12 29 SA14 12 14 21 29 SD1 12 14 29 SD7 12 14 29 DRQ1 13 14 29 SA13 12 14 21 29 IRQ12 13 14 29 REFRESH 12 29 SD6 12 14 29 DACK 3 13 14 BRSTDRV 26 LA17 12 29 SD8 12 29 DRQ6 13 29 DRQ2 13 14 29 SA8 12 14 21 29 ZEROWS 12 29 DACK 2 13 14 DACK 6 13 SA7 12 14 ...

Page 105: ...DD0 1 R_PDDREQ R_PDIOR RPDACK R_PDA1 PDA1 R_PCS3 PDA2 PDA0 R_PDA2 R_PCS1 PDD8 SDD8 2 SDD5 2 SDD4 2 SDD11 2 SDD12 2 SDD1 2 SDD0 2 SDD15 2 SDA2 VCC VCC VCC VCC RP103 33 1 8 2 7 3 6 4 5 RP96 33 1 8 2 7 3 6 4 5 J28 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 35 37 39 36 38 40 RP97 33 1 8 2 7 3 6 4 5 RP90 33 1 8 2 7 3 6 4 5 RP89 33 1 8 2 7 3 6 4 5 R140 4...

Page 106: ...BD1 UGND0 USBV0 USBD1 USBD1 USBD0 USBG0 USBV1 USBG1 USB_PWR0 R_USBD1 VCC VCC R122 27 C247 47pF C12 1uF R13 560K R110 15K R123 27 L4 BLM31A700S 2 1 C32 68 uF R12 560K R124 27 R109 0 L6 BLM31A700S 2 1 R106 15K R15 470K R111 15K R121 27 C41 0 001uF R113 0 R10 0 C14 0 1 uF R107 15K C3 1uF C30 0 001uF R108 0 C249 47pF C13 0 1 uF L1 BLM31A700S 2 1 C31 68 uF F1 1 5 2 0A L5 BLM31A700S 2 1 F3 1 5 2 0A L3 B...

Page 107: ...17 SA2 XD1 SA6 SA15 J_SA17 SA19 SA16 BIOSCS SA13 SA12 SA5 SA4 SA17 SA4 SA17 XD1 SA2 SA0 XD0 SA8 FL1MPU FL_VPP SA7 SA13 XD6 SA11 SA14 XD2 SA1 SA6 XD0 SA12 SA15 SA18 SA0 SA10 SA14 XD2 SA9 SA10 SA9 XD3 SA17 FL2MPU 12V VCC 12V C396 0 1 uF J41 1 3 2 U30F 74HCT14 13 12 J42 1 3 2 J27 Emulator Header 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 U26 E28F002BC...

Page 108: ...1 8 2 7 3 6 4 5 RP8 1K 1 8 2 7 3 6 4 5 RP6 1K 1 8 2 7 3 6 4 5 RP83 33 1 8 2 7 3 6 4 5 CP9A 180pF 1 8 CP3D 180pF 4 5 CP3C 180pF 3 6 CP3B 180pF 2 7 CP3A 180pF 1 8 CP5D 180pF 4 5 CP5B 180pF 2 7 CP5A 180pF 1 8 CP6D 180pF 4 5 CP6C 180pF 3 6 CP6B 180pF 2 7 CP6A 180pF 1 8 CP4D 180pF 4 5 CP4C 180pF 3 6 CP4B 180pF 2 7 CP4A 180pF 1 8 RP84 33 1 8 2 7 3 6 4 5 RP85 33 1 8 2 7 3 6 4 5 RP10 1K 1 8 2 7 3 6 4 5 CP...

Page 109: ...25 26 27 28 29 30 31 32 33 34 TP92 1 RP111 1K 1 8 2 7 3 6 4 5 CP8A 100pF 1 8 CP8B 100pF 2 7 CP8C 100pF 3 6 CP7B 100pF 2 7 CP7C 100pF 3 6 CP7D 100pF 4 5 J4 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 CP8D 100pF 4 5 CP7A 100pF 1 8 CP2C 100pF 3 6 CP2D 100pF 4 5 J1 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 U6 GD75232SOP 1 20 11 10 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 VCC VCC GND VCC RA RA RA DY DY RA DY RA...

Page 110: ...er Rev Date Sheet of TP097 KB5V_FB KBDAT_FB MSCLK_FB KBSIGND KBCLK_FB TP096 MSCLK_FB MSDAT_FB TP095 KBSIGND KB5V_FB TP098 KBCLK_FB KBSHGND VCC L10 FBHS04B 2 1 C33 470pF C44 470pf C43 470pF TP094 1 TP093 1 TP095 1 TP096 1 F2 1 25A L12 FBHS01K 2 1 C35 470pF C34 470pF J6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 L9 FBHS01K 2 1 L11 FBHS01K 2 1 L8 FBHS01K 2 1 L...

Page 111: ...9 1 0 uF C378 1 0 uF CERAMIC X7R R240 1 30K 1 C197 1 uF C208 100uF Q6 MMFT3055EL 2 1 3 4 U15A 74F07 1 2 R241 10 U17 74LVC3244 2 4 6 8 11 13 15 17 1 19 18 16 14 12 9 7 5 3 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 R95 100 C198 1 uF C412 2200pF R220 1 21K 1 C221 100uF U37 LT1575_0 1 2 5 3 1 4 6 7 8 VIN COMP GND S D FB GATE INEG IPOS C229 1 uF U20 LT1585A 1 5 3 2 1 VIN VOU...

Page 112: ... 2 R216 10K C343 4 7NF R84 4 7K R233 4 7K R38 1 5K R243 68 1 2 C402 0 1uF 1 2 R225 2 2K 1 2 J22 640456 3 1 2 3 C74 1uF R245 220 C372 100pF U31A 74F06 1 2 R187 100 C404 470 pF J46 R230 330 R242 68 1 2 Q8 MMBT3904L J9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 R203 10K R23 330 U30C 74HCT14 5 6 BZ1 SPEAKER 1 2 1 2 Q2 P FET SI9933DYS C344 22uF R232 240 U30E 74HCT14 11 10 U32A 74HC10 1 2 13 12 ...

Page 113: ... HREQ 0 HREQ 3 HREQ 4 HREQ 2 HA 29 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT RP56 56 ohm 1 8 2 7 3 6 4 5 RP44 56 ohm 1 8 2 7 3 6 4 5 RP28 56 ohm 1 8 2 7 3 6 4 5 RP29 56 OHM 1 8 2 7 3 6 4 5 RP64 56 ohm 1 8 2 7 3 6 4 5 RP39 56 ohm 1 8 2 7 3 6 4 5 RP36 56 ohm 1 8 2 7 3 6 4 5 RP53 56 OHM 1 8 2 7 3 6 4 5 RP73 56 ohm 1 8 2 7 3 6 4...

Page 114: ...2 3 4 5 6 7 8 RP70 8 2K 1 2 3 4 5 6 7 8 RP27 8 2K 1 2 3 4 5 6 7 8 RP62 10K 1 2 3 4 5 6 7 8 RP17 330 1 2 3 4 5 6 7 8 R45 220 RP109 10K 1 2 3 4 5 6 7 8 RP95 10K 1 2 3 4 5 6 7 8 RP71A 2 2K 1 8 PHLDA 7 12 A20M 3 25 FRAME 7 12 16 17 PREQ 4 7 GPAR 7 15 34 STOP 7 12 16 17 BATLOW 13 LINT1 3 25 PICD 1 0 3 PX4_IGNNE 13 25 PX4_CFG1 13 AGP_PME 13 15 PIRQ A 13 15 16 17 34 SMBALERT 13 THERM 3 13 SMBCLK 3 6 9 10...

Page 115: ... 3 6 4 5 RP13 10K 1 8 2 7 3 6 4 5 RP74 10K 1 8 2 7 3 6 4 5 RP75 10K 1 8 2 7 3 6 4 5 R126 1K RP79 1K 1 8 2 7 3 6 4 5 R26 1K RP3 4 7K 1 8 2 7 3 6 4 5 U34A 74F07 1 2 14 7 TP4403 1 U32B 74HC10 3 4 5 6 14 7 TP148 1 U36D 74F07 9 8 14 7 U36F 74F07 13 12 14 7 U36A 74F07 1 2 14 7 U36E 74F07 11 10 14 7 U36C 74F07 5 6 14 7 U31B 74F06 3 4 U31C 74F06 5 6 TP151 1 TP149 1 TP4407 1 TP4400 1 TP4401 1 TP141 1 TP142...

Page 116: ... 1 uF 16 C118 22uF 10V C40 22uF 10V C22 22uF 16V C34 22uF 10V C14 22uF 10V C24 22uF 10V C18 22uF 10V C195 1 uF 16 C236 1 uF 16 C252 1 uF V C279 1 uF 16V C329 1 uF 16V C219 1 uF 16V C235 0 01 uF 16 C385 0 01 uF 16 C92 0 01 uF 16 C319 0 01 uF 16 C317 0 01 uF 16 C99 0 01 uF 16V C113 0 01 uF V 0 01 uF 16V C10 0 01 uF 16V C36 0 01 uF 16 C386 0 01 uF 16 C70 0 01 uF 16 C39 0 01 uF 16 C405 0 01 uF 16 C243...

Page 117: ...C251 0 01 uF 16V C153 0 01 uF 16V C138 0 01 uF 16V C137 0 01 uF 16V C136 0 01 uF 16V C303 0 01 uF 16V C276 0 01 uF 16V C274 0 01 uF 16V C202 0 01 uF 16V C107 0 01 uF 16V C383 0 01 uF 16V C109 0 01 uF 16V C38 0 01 uF 16V C108 0 01 uF 16V C169 0 01 uF 16V C152 0 01 uF 16V C245 0 01 uF 16V C176 0 01 uF 16V C168 0 01 uF 16V C285 0 01 uF 16V C278 0 01 uF 16V C218 0 01 uF 16V C241 0 01 uF 16V C384 0 01 ...

Page 118: ...er Rev Date Sheet of VTT VTT VTT C199 0 01 uF 16V C173 0 01 uF 16V C124 1 uF 16V C132 0 01 uF 16V C151 0 01 uF 16V C128 0 01 uF 16V C129 0 01 uF 16V C175 0 01 uF 16V C116 0 01 uF 16V C150 0 01 uF 16V C145 0 01 uF 16V C131 0 01 uF 16V C207 0 01 uF 16V C147 22 pF 16V C148 0 01 uF 16V C171 0 01 uF 16V C170 0 01 uF 16V C123 0 01 uF 16V C184 0 01 uF 16V C130 0 01 uF 16V C196 0 01 uF 16V C146 0 01 uF 16...

Page 119: ... 39 13 16 35 22 37 21 24 20 36 34 2 19 3 18 11 12 10 9 8 7 6 5 4 44 43 41 42 14 15 38 17 33 32 31 30 29 28 23 27 26 25 SMI IORD NMI IRQ VSSD PS_BYPASS VID2 RESET VID0 SDA VSSA SCL VID1 VID3 IOWR FAN1 SYSCLK FAN2 D0 VCC5 D1 D2 D3 D4 D5 D6 D7 CS A0 A2 A1 SMI_IN CHASIS_INTRU BTI FAN3 IN0 IN1 IN2 IN3 IN4 IN5 VID4 NTEST FB5 FB6 IN6 R183 10K R209 232K R184 10K R210 66 5K R228 100K R229 10K R206 100K R20...

Page 120: ...02 L04 K01 F02 H01 J04 J02 J03 K03 K05 K02 K04 G03 G04 R05 T03 R04 T01 R03 T02 G02 H05 D21 L25 AA02 B17 A17 D16 C16 B16 H02 J01 W01 M01 R02 J23 L11 L12 VCC VP15 VCC VCC VSS VRDY VCCA VCC VSS VCCP VCC HREF VCC VSS VCC VCCA VCC VREF VCC VSS VCC VCLK VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS VSS VSSA VSS VSS VSSA VSS VSS VSS VSS VCCP VSS VCCP VSS VCCP VDDQ VSS VSS VSS VSS VSS VSS VS...

Page 121: ...T24 AF10 R26 W25 P24 V23 AD11 P25 AF16 N24 AE11 P26 N23 R22 N26 AC17 M24 T25 M26 M23 R23 M25 AE16 M22 T26 L26 AD18 AF17 AD13 AC18 AE17 AD19 AF18 AC19 AE18 AD06 AC16 AF12 AD14 AE06 AE13 AD15 AC07 AF13 AC15 AF06 AF14 AD16 AD07 AF15 AF07 AC08 AE07 AD08 AF08 AC09 AE09 AD09 AF09 AC10 AE10 AC12 AF11 AD12 AE12 AA23 H23 AE19 AF19 AF20 AE20 AD20 AC20 AA25 AA26 Y23 Y24 F24 F26 G24 J25 J26 K26 K25 C21 F01 F0...

Page 122: ... Number Rev Date Sheet of L_RED L_GREEN L_BLUE MON2PU FUSE_5 MON0PU VGA_HSYNC VGA_VSYNC 5VDDCCL VCC VCC VCC VCC3 VCC3 C25 22PF C8 22PF C26 22PF C9 22PF C27 22PF C10 22PF FB1 FB 1 2 FB2 FB 1 2 FB3 FB 1 2 R4 1K R9 75 R18 75 R19 75 t R5 THERMISTOR R1 1K R3 0 R2 0 CR5 BAV99 1 2 3 CR4 BAV99 1 2 3 CR1 BAV99 1 2 3 CR2 BAV99 1 2 3 CR3 BAV99 1 2 3 J3 VGA CONN 6 5 15 10 4 14 9 3 13 8 2 12 7 1 11 RED 35 GREE...

Page 123: ...ND NC GND NC GND GND NC GND NC GND NC GND NC NC GND NC GND NC GND VCC3 GND VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 NC NC NC NC NC NC NC NC NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AP A10 BA DQM0 DQM1 DQM2 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CLK VDDQ VREF MCH NC DRDY CKE CS RAS CAS WE...

Page 124: ...25 1 2 4 5 13 12 10 9 7 14 3 6 11 8 A_0 BO A_1 B1 A_2 B2 A_3 B3 GND VCC D0 D1 D2 D3 U4A Q_NAND 1 2 3 14 7 U4B Q_NAND 4 5 6 U5A 12 11 10 9 8 13 14 7 D CLK PRE Q NQ CLR VCC GND RP1D 4 5 U5B 2 3 10 5 6 1 14 7 D CLK PRE Q NQ CLR VCC GND U2 74LVT244_1 2 4 6 8 17 15 13 11 18 16 14 12 3 9 5 7 1 19 20 10 I0 I1 I2 I3 I4 I5 I6 I7 D0 D1 D2 D3 D4 D7 D5 D6 OE_1 OE_2 VCC GND U4C Q_NAND 9 10 8 PCIRST 6 12 15 16 ...

Page 125: ...e Size Document Number Rev Date Sheet of QSV QSV QSV VCC VCC QS3861 U7 QS3861 24 12 22 10 21 2 20 11 19 3 18 4 17 5 16 6 15 7 14 8 13 9 23 1 QSV GND B0 A8 B1 A0 B2 A9 B3 A1 B4 A2 B5 A3 B6 A4 B7 A5 B8 A6 B9 A7 BE NC RP4B 10K 2 7 RP4A 10K 1 8 RP5A 2 2K 1 8 RP5B 2 2K 2 7 C18 01UF C19 1UF R7 10K R6 1 62K 5VSCL 5VSDA 5VDDCDA 36 5VDDCCL 36 3VSCL 35 3VSDA 35 3VDDCDA 35 3VDDCCL 35 ...

Page 126: ...R INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD FM5 79 FOLSOM CA 95630 Custom 40 41 22 16 57 Title Size Document Number Rev Date Sheet of L_GATE COMP1 FB1575 R_GATE M_COMP1 VCC_REGULATED 2_7V VCC3 12V 2_7V C24 22UF C82 10UF C102 1UF C81 1UF C139 01UF C111 01UF C120 1UF C100 1UF C122 01UF C121 01UF C112 1UF C101 01UF U9 LT1575 1 2 3 4 5 6 7 8 SHDN VIN GND FB COMP GATE INEG IPO...

Page 127: ...release of 3 Device AGP schematics REVISION1 0 8 98 3 DEVICE AGP 1 0 INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD FM5 79 FOLSOM CA 95630 Custom 41 41 REVISION HISTORY 22 16 57 Title Size Document Number Rev Date Sheet of ...

Page 128: ...4 Thermal Considerations ...

Page 129: ......

Page 130: ...r the thermal solution may change The following table lists the design considerations which must be made For a comprehensive guide to thermal design please refer to Application Note 653 Thermal Design Considerations This application note is provided in Appendix B of this document Table 4 1 Thermal Design Considerations Chart Intel740 Graphics Accelerator Usage Design Considerations Designing for R...

Page 131: ...Thermal Considerations 4 2 Intel740 Graphics Accelerator Design Guide ...

Page 132: ...5 Mechanical Information ...

Page 133: ......

Page 134: ... the capability of attaching a fansink If a design requires a fansink the following design issues must be observed to be compatible with the fan attach mechanism Intel has enabled The mounting holes must be nonplated but each must have a grounded annular ring on the solder side of the board surrounding the hole This annular ring should have an inner diameter of 150 mils and an outer diameter of 30...

Page 135: ...of the card For other designs these headers may be placed at the top of the board The latter is recommended for an NLX card Note Z1 Connectors in Figure 5 3 are on the backside of the card Figure 5 2 VMI Header Placement 0 200 min 0 300 Board Edge 40 pin conn 26 pin conn Z1 Z1 Figure 5 3 DVD Daughter Card Dimensions ATX and NLX Top Side 0 200 min 0 300 Z1 Z1 200 min 2 05 max 0 355 max 1 945 max 0 ...

Page 136: ...t exceeds these dimensions underneath the daughter card the daughter card may not fit 5 4 50 Pin Video Connector The following diagram is a pinout view of the 50 pin video connector illustrating the different video connections which can exist Figure 5 4 50 Pin Video Connector Schematic 1 GND 2 GND 3 CVBS 4 NC 5 I2CSCK 6 12V 7 I2CSDATA 1 GND 2 GND 3 Y 4 C 1 2 3 4 5 6 7 1 2 3 4 1 GND 2 GND 3 Y 4 C 1...

Page 137: ...Mechanical Information 5 4 Intel740 Graphics Accelerator Design Guide 5 5 Bracket Figure 5 5 Recommended Bracket Placement Figure 5 6 Recommended Bracket Cutout ...

Page 138: ...rd can be used in an ATX chassis but needs to use an ATX bracket Unless a dual sided board is used the full featured reference design will not be feasible on the NLX add in card This is due to the decreased physical size of the NLX add in card The 50 pin video connector will not fit in the NLX chassis Each board designer must determine the placement of their desired features on the NLX card ...

Page 139: ...Mechanical Information 5 6 Intel740 Graphics Accelerator Design Guide ...

Page 140: ...6 Third Party Vendors ...

Page 141: ......

Page 142: ...Voltage Regulator Linear Technology Todd Jackson 408 428 2061 6 2 50 Pin Connector Foxconn P N QA11253 58 6 3 Fan Heatsink Sanyo Denki James Sia 310 212 7724 Fan Heatsink P N 109P4405H9026 Clip prototype XF 8300 Clip production 109 688 6 4 Flash Components Intel 28F010 28F001 6 5 Video Encoders Decoders Rockwell Semiconductor Tim Yates 619 535 3522 Video Encoder Bt868 869 Video Decoder Bt829a ...

Page 143: ...ma Designs Ron Berti 510 770 2691 Toshiba Elie Semaan 408 965 4266 Zoran Jack Koplik 408 919 4237 6 7 TV Tuner Hauppauge Computer Works Inc 91 Cabot Court Hauppauge NY 11788 Phone 516 434 1600 Fax 516 434 3198 Web Site www hauppauge com Contact name Bob Rosoff brosoff hauppauge com Model 5901 4 1x4 2 ISA form factor NTSC systems M N tuner card The only contacts on the ISA bus are for power supply ...

Page 144: ...A Application Notes ...

Page 145: ...Intel740 Graphics Accelerator Application Note 653 Thermal Design Considerations April 1998 Order Number 292211 002 ...

Page 146: ...ns and product descriptions at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order The Intel740 graphics accelerator may contain design defects or errors known as errata which may cause the products to deviate from published specifications Such errata are not covered by Intel s warranty Current ...

Page 147: ...10 4 2 1 Clearance 10 4 2 2 Low Profile Fan Heat Sink 11 4 2 2 1 Low Profile Fan Heat Sink PCB Layout Guidelines 11 4 2 2 2 Low Profile Fan Heat Sink Electrical Requirements 12 4 2 2 3 Low Profile Fan Heat Sink Attach 13 4 2 2 4 Low Profile Fan Heat Sink Reliability 13 4 2 3 Low Profile Passive Heat Sink 14 4 2 3 1 Clip Attach 14 4 2 3 2 Epoxy 14 4 2 3 3 Tape Attach 15 4 2 3 4 Reliability 17 4 3 T...

Page 148: ...2 6 Fan Heat Sink Connector Design 13 7 Tape Layers 15 8 Attaching the Tape to the Package and Heat Sink 15 9 Completing the Attach Process 16 10 Technique for Measuring Tcase with 0 Angle Attachment 20 11 Technique for Measuring Tcase with 90 Angle Attachment 20 12 Thermal Enhancement Decision Flowchart 21 Tables 1 Intel740 Graphics Accelerator Preliminary Thermal Absolute Maximum Rating 3 2 Defa...

Page 149: ...740 graphics accelerator is the newest addition to the growing market of fast 3D graphics accelerators Previous generations of graphics accelerators generated insufficient heat to require an enhanced cooling solution in order to meet the case temperature specifications in system designs As the market transition to higher speeds with enhanced features the heat generated by these advanced graphics a...

Page 150: ...die and molding compound Lands Pads on the PCB where BGA Balls are soldered Mold Cap The black encapsulating molding compound The top of this is where maximum case temperatures are taken and where heat sinks are attached PCB Printed Circuit Board STBGA Super Thermal BGA A Ball Grid Array Package enhanced to improve its thermal characteristics The Intel740 graphics accelerator uses this type of BGA...

Page 151: ...ns and vents along with their placement in relation to the components and the airflow channels within the system In addition acoustic noise constraints may limit the size and or types of fans and vents that can be used in a particular design To develop a reliable cost effective thermal solution all of the above variables must be considered Thermal characterization and simulation should be carried ...

Page 152: ...nducts heat away from the package and whether the package uses thermal enhancements While package thermal enhancements typically serve to improve heat flow through the case via a heat sink how well the motherboard conducts heat away from the package is strictly a function of motherboard design The following should be taken into account by system designers when developing new systems How well the t...

Page 153: ...minimize the heating effects of other system components and to eliminate excessive warm air re circulation For example a clear air path from the external system vents to the system fan s will enable the warm air from the Intel740 graphics accelerator and AGP Card to be efficiently removed from the system If no air path exists across the them the warm air ambient to the Intel740 graphics accelerato...

Page 154: ...ons 6 Application Note 653 Figure 1 Example of air exchange through a PC chassis Power Supply CPU Vent Cards Drive Bay Fan intake Fan exhaust Good Air Exchange Power Supply CPU Cards Drive Bay Vent Fan intake Poor Air Exchange Little Airflow or Recirculated ...

Page 155: ...fficiency of heat transfer from the device to the motherboard 4 1 1 Fan Placement Proper placement of the fans can ensure that the Intel740 graphics accelerator is properly cooled Because of the difficulty in building measuring and modifying a mechanical assembly models are typically developed and used to simulate a proposed prototype for thermal effectiveness to determine the optimum location for...

Page 156: ...sis Top View Figure 3 Fan Placement and Layout of an NLX Form Factor Chassis Top View AGP Slot Motherboard Peripherals Required Fan Power Supply Fan PCI Slot ISA Slot Power Supply Vent Fan PS Exhaust Fan Passive SECC Fan Backplane AGP Slot Mother board Fan Vent Passive SECC Vent Vent Peripherals Vent Fan Power Supply Required Vent Required Fan ...

Page 157: ...ver as system configurations vary testing the target configuration to verify the benefit is recommended 4 1 4 Fan Venting As shown in Figure 2 and Figure 3 intake venting should be placed at the front user side of the system Location should take into consideration cooling of the microprocessor and peripherals as well as the Intel740 graphics accelerator A good starting point would be the lower 50 ...

Page 158: ...he Intel740 graphics accelerator and card 4 2 Thermal Enhancements One method used to improve thermal performance is to increase the surface area of the device by attaching a metallic heat sink to the mold cap To maximize the heat transfer the thermal resistance from the heat sink to the air can be reduced by maximizing the surface area of the heat sink itself For users whose ambient environments ...

Page 159: ... Layout Guidelines As the Low Profile Fan Heat Sink uses a mechanical attach mounting holes must be provided in the PCB to accommodate the clips necessary in attaching the Fan Heat Sink PCB Guidelines for the Fan Heat Sink mounting hole layout are provided in Figure 5 The mounting holes must be non plated but each must have a grounding pad on the solder side of the board surrounding the hole It mu...

Page 160: ... mate with a receptacle attached to a power cable that will be installed by the graphics card manufacturer See Figure 5 The Fan Heat Sink assembly when installed in at least one typical host application should not cause an increase in emissions above that measured from the host application before the assembly was installed The signal pin on fan header may supply an open collector rotor lock output...

Page 161: ...4 0 C per Watt at 80 of nominal fan RPM in a worst case system environment defined as zero airflow 55 C internal ambient temperature 4 2 2 4 Low Profile Fan Heat Sink Reliability As every motherboard system heat sink and attach process combination may introduce variance in attach strength and the use of a fan heat sink adds the need for fan lifetime evaluation it is generally recommended that the ...

Page 162: ...ening for these holes should have a radius of 300 mils As clip designs are generally unique to a specific system and board layout no procedural comments are provided 4 2 3 2 Epoxy Some users may prefer to implement Epoxy attaches for their thermal solution For these users products known to be compatible with the mold cap material are listed in Appendix A Epoxy users should plan their process caref...

Page 163: ...When in this temperature range the heat sink can safely be removed from the component without damaging it 4 2 3 3 Tape Attach For users who prefer to attach via Tape please refer to Section A Sources on page 23 for the suggested manufacturer and part number To maximize the bond line contact area and improve adhesion we recommend using two pieces of tape one attached to the heat sink and one attach...

Page 164: ...roper safety precautions and Isopropyl Alcohol to ensure cleanliness 2 Cut tape to size Suggestions for the appropriate size can be seen in Figure 8 3 Heat Sink Side Remove the non transparent liner You will see foil underneath Figure 7 Apply the tape to the center of the heat sink and smooth over the entire surface using moderate pressure There should be no air bubbles under the tape 4 Component ...

Page 165: ...ns For solutions where a heat sink is preferred to optimize the heat sink design for Intel740 graphics accelerator it is important to understand the impact of factors related to the interface between the mold cap and the heat sink base Specifically the bond line thickness interface material area and interface material thermal conductivity should be managed to realize the most effective heat sink s...

Page 166: ...erformance of the interface material between the thermal plate and the heat sink base Thermal resistance of the material Wetting filling characteristics of the material Thermal resistance is a description of the ability of the thermal interface material to transfer heat from one surface to another The higher the thermal resistance the less efficient an interface is at transferring heat The thermal...

Page 167: ...ocal ambient air errors could be introduced in the measurements The measurement errors could be due to having a poor thermal contact between the thermocouple junction and the surface of the package heat loss by radiation convection by conduction through thermocouple leads or by contact between the thermocouple cement and the heat sink base for those solutions which implement a heat sink To minimiz...

Page 168: ...sed bandwidth To ensure the thermal performance of the Intel740 graphics accelerator while running future applications Intel has developed a software utility which emulates this anticipated power dissipation The power simulation software has been developed only for testing Thermal Design Power Real future applications may exceed the Thermal Design Power limit for transient time periods For power s...

Page 169: ...ples as described in Section 5 1 Setup system in desired worst case configuration drives cards memory etc Run the Power Software while monitoring the Intel740 graphics accelerator case temperature Tcase X C No Yes Heat Sink Not Required Heat Sink Required See Section 4 2 Select Heat Sink See Section 4 2 Attach Thermocouples as described in Section 5 1 Setup system in desired worst case configurati...

Page 170: ...ired thermal enhancements in conjunction with enhanced system cooling The size of the fan or heat sink can be varied to balance size and space constraints with acoustic noise This document has presented the conditions and requirements for properly designing a cooling solution a system implementing the Intel740 graphics accelerator Properly designed solutions provide adequate cooling to maintain th...

Page 171: ...ase visit WEB at http www thermalloy com JME please visit WEB at http www jme com Part Numbers Thermalloy 2522B JME HAA740BBXXB 001 with 1 layer Chomerics T410 HAA740BBXXX 001 without attach A 3 Attach Sales Locations For Epoxy please visit WEB http www loctite com Select the country of your choice and Select Products for the Electronics Industry For Tape please visit WEB http www chomerics com lo...

Page 172: ...Intel740 Graphics Accelerator Thermal Design Considerations 24 Application Note 653 ...

Page 173: ...fic Place 88 Queensway Central Hong Kong Tel 852 844 4555 JAPAN Intel Japan K K 5 6 Tokodai Tsukuba shi Ibaraki 300 26 Japan Tel 81 298 47 8511 SOUTH AMERICA Intel Semicondutores do Brazil LTDA Rua Florida 1703 2 and CJ 22 04565 001 Sao Paulo SP Brazil Tel 55 11 5505 2296 FOR MORE INFORMATION To learn more about Intel Corporation visit our site on the World Wide Web at http www intel com Other bra...

Page 174: ......

Page 175: ...Intel740 Graphics Accelerator Application Note 3 Device AGP System BIOS Design Guidelines August 1998 Order Number 290628 001 ...

Page 176: ...ations and product descriptions at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order The Intel740 graphics accelerator may contain design defects or errors known as errata which may cause the products to deviate from published specifications Such errata are not covered by Intel s warranty Curr...

Page 177: ...or and Mulitmonitor Configurations 4 2 3 Software Sequence 4 Figures 1 Schematic Diagram for GPO27 2 2 Schematic Diagram for GPO28 2 3 Intel740 Graphics Controller On board Device Remains in Low Power Mode 3 4 Intel740 Graphics Controller On board Device State Diagram 3 Tables 1 Signal Duration of the GPO Signals from PIIX4 2 2 Monitor and Mulitmonitor Configurations 4 ...

Page 178: ......

Page 179: ...tegrator or OEM to manually disable the on board Intel740 chip and bypass any enabling events 2 0 Low Power Mode Overview Two signals GPO27 and GPO28 from the PIIX4E are used in this design These GPOx signals must be asserted by the system BIOS GPO28 is needed to put the Intel740 chip in low power mode This signal must be asserted sometime after the trailing edge of system RESET See Figure 2 GPO27...

Page 180: ...device desired 3 Multimonitor configurations not utilizing the on board graphics device For example 2 and 3 above an option should be provided in system BIOS or CMOS setup to keep the Intel740 chip in low power mode Note When not in use both GPO27 and GPO28 should be driven high 1 Figure 1 Schematic Diagram for GPO27 PIIX4E PCIRST GPO27 Vcc3 D Q Q PCICLK3 Vcc3 OE IN1 OUT1 ROMA16 RESET Intel740 Chi...

Page 181: ...he low power mode see Figure 4 The following are examples in which functional mode would be invoked 1 Intel740 graphics accelerator as the primary and only graphics device 2 Multimonitor configurations utilizing the Intel740 graphics controller Figure 3 Intel740 Graphics Controller On board Device Remains in Low Power Mode Figure 4 Intel740 Graphics Controller On board Device State Diagram System ...

Page 182: ...evice 1 AGP Bridge go to step 8 6 Assert GP028 low for at least 1us 7 Assert GP028 high the Intel740 Graphics Controller on board device is in a normal operating state after executing this instruction 8 Re program the 82443BX Device 1 AGP Bridge to disable the access to devices behind the bridge 9 Continue with rest of POST in BIOS Table 2 Monitor and Mulitmonitor Configurations Configuration Sing...

Page 183: ......

Page 184: ...etherlands 31 10 286 6111 Sweden 46 8 705 5600 Asia Pacific Intel Semiconductor Ltd 32 F Two Pacific Place 88 Queensway Central Hong Kong SAR Phone 852 2844 4555 Japan Intel Kabushiki Kaisha P O Box 115 Tsukuba gakuen 5 6 Tokodai Tsukuba shi Ibaraki ken 305 Japan Phone 81 298 47 8522 South America Intel Semicondutores do Brazil Rua Florida 1703 2 and CJ22 CEP 04565 001 Sao Paulo SP Brazil Phone 55...

Page 185: ...B Reference Information ...

Page 186: ......

Page 187: ...PC SGRAM Specification Revision 0 9 February 1998 Order Number Not Applicable ...

Page 188: ...OUT OF ANY PROPOSAL SPECIFICATION OR SAMPLE Intel disclaims all liability including liability for infringement of any proprietary rights relating to use of information in this specification No license express or implied by estoppel or otherwise to any intellectual property rights is granted herein Copyright Intel Corporation 1996 1997 Third party brands and names are the property of their respecti...

Page 189: ... 4 NOP and Device Deselect 15 7 5 Row activate 15 7 6 Read Bank 15 7 7 Write Bank 15 7 8 Block Write 16 7 9 Mode Register Set 16 7 10 Power Down Mode 17 8 0 Essential Functionality for the PC SGRAM device 18 8 1 Burst Read and Burst Write 18 8 2 Multi bank ping pong access 18 8 3 Read and Write with autoprecharge 18 8 3 1 Precharge Command After a Burst Read 18 8 3 1 1 Precharge Termination of a B...

Page 190: ...M Pinout 2 2 512kx32 SGRAM Pinout 3 3 Power Up Initialization Sequence 14 4 Mode Register Set Command 16 5 Timing for Power Down Mode 17 6 A C Timing Parameters 24 Tables 1 Pin Functional Description 4 2 Mode Register Description 5 3 Special Mode Register 5 4 Color Register 6 5 Command Truth Table 7 6 DQM Truth Table 7 7 Operative Command Table 8 8 Row Column and Bank addressing 13 9 Absolute Maxi...

Page 191: ... the main stream volume desktop Graphics architecture PCs 1 2 Scope of This Document The scope of this document is limited to identify and define all the essential functionality that is needed to be implemented for PC SGRAM Implementation details are left to the designers of the device 1 3 Convention Used sign after signals are used after the signal names for active low signals e g CS RAS etc ...

Page 192: ...2 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 6 7 8 9 10 DQ3 VddQ VssQ VddQ DQ16 DQ17 VssQ DQ18 DQ19 VddQ Vdd DQ20 DQ21 VssQ VddQ DM2 WE CAS RAS CS A9 BS NC Vss DQ4 DQ5 DQ6 DQ7 DQ22 DQ23 DM0 A7 A6 A5...

Page 193: ...6 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 6 7 8 9 10 DQ3 VddQ VssQ VddQ DQ16 DQ17 VssQ DQ18 DQ19 VddQ Vdd DQ20 DQ21 VssQ VddQ DM2 WE CAS RAS CS A10 BS A9 A8 Vss DQ4 DQ5 DQ6 DQ7 DQ22 DQ23 DM0 A7 A6 A5 A4 Vss NC Vdd A3 A2 A1 A0 NC NC NC ...

Page 194: ...es or enables the device operation by masking or enabling all inputs except CLK CLK CKE DQS DQ and DM RAS Input Synchronous Row address strobe CAS Input Synchronous Column address strobe WE Input Synchronous Write Enable DQM 3 0 Input DQ Mask Write data byte mask Read output byte enables Active high Read latency is two cycle from DQM and zero cycle for write In write mode it masks the data from be...

Page 195: ...be loaded into the Color and Mask registers Table 2 Mode Register Description Bit Attribute Description BA Reserved Reserved For normal operation BA 1 0 should be 0 A 9 7 Reserved Reserved For normal operation A 9 7 should be 000 A 6 4 WO CAS Latency 000 Reserved 001 Reserved 010 2 011 3 100 Reserved 101 Reserved 110 Reserved 111 Reserved A 3 0 WO Burst Type 0 Sequential 1 Interleave A 2 0 WO Burs...

Page 196: ... bit A 6 is used to determine if a new value is to be loaded into the Mask registers If A 6 1 during the special mode register command then the value on DQ 31 0 is loaded into the Color Register The color register supplies data for the block write command Table 4 Color Register Bit Default Attribute Description 31 0 00000000h WO Color Register Data Data from these bits is used for Block Write Comm...

Page 197: ...ck Write BLKWR L H L L H x v Column Address Bank Address Write WRITE L H L L L x v Column Address Bank Address Write with Auto precharge WRITEAP L H L L L H v Column Address Bank Address Read READ L H L H L L x Column Address Bank Address Read with Auto precharge READAP L H L H L H x Column Address Bank Address Burst Stop BST L H H L L x x x x Prechargeselect Bank PRE L L H L L L x x Bank Address ...

Page 198: ...e SMRWR Special Mode Register Write Row active H X X X X X DSEL NOP L H H H L X NOP NOP L H L H L BA CA A8 A9 READ READAP Begin read Optional AP 6 L H L L L BA CA A8 A9 WRITE WRITEAP Begin write Optional AP 6 L H L L H BA CA BLKWR Begin Block write 6 L L H H L BA RA ACT ILLEGAL 4 L L H L L BA A8 A9 PRE PALL Precharge 7 L L L H L X CBR SELF ILLEGAL 14 L L L L L OP code MRS ILLEGAL 14 L L L L H OP c...

Page 199: ...g 10 L L L H L X CBR SELF ILLEGAL 14 L L L L L Op Code MRS ILLEGAL 14 L L L L H Op Code SMRWR ILLEGAL 14 Read with auto precharge H X X X X X DSEL Continue burst to end precharging L H H H L X NOP Continue burst to end precharging L H L H L BA CA A8 A9 READ READAP ILLEGAL 13 L H L L L BA CA A8 A9 WRIT WRITEAP ILLEGAL 13 L H L L H BA CA BLKWR ILLEGAL 13 L L H H L BA RA ACT ILLEGAL 4 13 Current stat...

Page 200: ...GAL 4 13 L H L L H BA CA BLKWR ILLEGAL 4 13 L L H H L BA RA ACT ILLEGAL 4 13 L H H L L X BST ILLEGAL L L H L L BA A8 A9 PRE PALL NOP Enter Idle after Trp L L L H L X CBR SELF ILLEGAL 14 L L L L L Op Code MRS ILLEGAL 14 L L L L H Op Code SMRWR ILLEGAL 14 Row activating H X X X X X DSEL NOP Enter row active after Trcd L H H H L X NOP NOP Enter row active after Trcd L H L H L BA CA A8 A9 READ READAP ...

Page 201: ...rge after Tdpl L H H H L X NOP NOP Enter precharge after Tdpl L H L H L BA CA A8 A9 READ READAP ILLEGAL 4 9 13 Current state CS RAS CAS WE DSF Address Command Action Notes L H L L L BA CA A8 A9 WRIT WRITEAP ILLEGAL 4 13 L H L L H BA CA BLKWR ILLEGAL 4 13 L L H H L BA RA ACT ILLEGAL 4 13 L H H L L X BST ILLEGAL L L H L L BA A8 A9 PRE PALL ILLEGAL 4 14 L L L H L X CBR SELF ILLEGAL 14 L L L L L Op Co...

Page 202: ...e 6 Illegal if trcd is not satisfied 7 Illegal if tras is not satisfied 8 Must satisfy burst interupt condition 9 Must satisfy bus contention bus turn around and or write recovery requirements 10 Must mask preceding data which don t satisfy tdpl 11 Illegal if trrd is not satisfied 12 Burst Stop command is disabled 13 Ilegal for single bank but legal for other banks in multi bank devices 14 Illegal...

Page 203: ...6 0 Row Column Addressing Per Memory Size Banks Table 8 Row Column and Bank addressing Parameter 2x128kx32 8Mb 2x256kx32 16Mb Bank Address BA BA Row Address A 8 0 A 9 0 Column Address A 7 0 A 7 0 Auto Precharge A8 A9 Page Size 256x32 256x32 ...

Page 204: ...alization sequence can be issued at anytime Following the initialization sequence the device must be ready for full functionality SGRAM devices are initialized by the following sequence At least one NOP cycle will be issued after the 1msec device deselect A minimum pause of 200usec will be provided after the NOP A precharge all PALL will be issued to the SGRAM 8 Auto refresh CBR refresh cycles wil...

Page 205: ...when CS is active and by deactivating RAS CAS and WE For both Deselect and NOP the device should finish the current operation when this command is issued 7 5 Row activate This command is used to select a row in a specified bank of the device Read and write operations can only be initiated on this activated bank after the minimum TRCD time is elapsed from the activate command 7 6 Read Bank This com...

Page 206: ... to execute No new commands can be executed until TWBC is met except for Activate and Precharge command to the other banks 7 9 Mode Register Set This command is used to program the SGRAM for the desired operating mode This command should be used after power up as defined in the power up sequence before the actual operation of the SGRAM is initiated The functionality of the SGRAM device can be alte...

Page 207: ...tput buffers are de activated except for CKE If the device stays in the power down mode for more than 15 6 usec refresh interval then the PC SGRAM will loose data The power down mode can be exited by driving CKE high again CKE assertion and de assertion should meet the CKE setup and hold time tCKS and tCKH Figure 5 Timing for Power Down Mode tCKS Input Buffers Gated Input Buffers Gated tCKS tCKH N...

Page 208: ...ctivate bank command and then the read or write command should be initiated Read and write is distinguished by the WE signal state as shown TRCD RAS to CAS delay must be met to initiate a command after the activate command 8 2 Multi bank ping pong access Two bank ping pong access is described in the following diagram Another bank can be activated while the first bank is being accessed as shown RAS...

Page 209: ...ned by TCCD 8 3 3 Write Terminated By Write A Write Command should terminate the previous write command and the new burst write command should start with the new command as shown Fastest command to command delay is determined by TCCD 8 3 4 Read Terminated By Write A Write Command should terminate the previous read command and the new burst write should start The DQM must be held active to keep the...

Page 210: ...supported 8 5 Auto Refresh CBR Command An auto refresh CBR should be used to refresh the SGRAM array explicitly Refresh addresses should be generated internally by the SGRAM device and incremented after each auto refresh automatically No commands including another auto refresh should be issued until a minimum TRC is satisfied ...

Page 211: ...r the table below Table 9 Absolute Maximum D C Rating Symbol Parameter Min Max Units Notes Vin Vout Voltage on any pin w r t VSS 0 5 VDD 0 5 V VDD VDDQ Voltage Supply pins pin w r t VSS 0 5 4 5 V Ts Storage Temperature 55 125 C Table 10 D C Operating Requirements Symbol Parameter Condition Min Max Units Notes VDD Supply Voltage 3 135 3 6 V VDDQ I O Supply Voltage 3 135 3 6 V Iil Input Leakage Curr...

Page 212: ...t delay max TAC max 7 6 6 5 5 ns Output data hold time TOH 2 5 2 5 2 5 2 5 ns Address Command Input setup time TAS 2 5 2 5 2 1 ns Address Command Input hold time TAH 1 1 1 1 ns Data Input setup time TDS 2 5 2 1 5 1 ns Data Input hold time TDH 1 1 1 1 ns Activate to Activate Delay Different bank TRRD 2 2 2 2 CLK Read to Read Command Delay Write to Write Command Delay TCCD 1 1 1 1 CLK Activate to Re...

Page 213: ...OH 2 5 TBD TBD ns Address Command Input setup time TAS 1 TBD TBD ns Address Command Input hold time TAH 1 TBD TBD ns Data Input setup time TDS 1 TBD TBD ns Data Input hold time TDH 1 TBD TBD ns Activate to Activate Delay Different bank TRRD 2 TBD TBD CLK Read to Read Command Delay Write to Write Command Delay TCCD 2 TBD TBD CLK Activate to Read Write or Block Write Delay TRCD 3 TBD TBD CLK Prechar...

Page 214: ...utput Buffers TBD NOTE 1 Reference level is set at 1 5V AC measurements are specified into 50pf load 2 input edge rates are specified as 1 0v ns minimum 0 8v to 2 0v Figure 6 A C Timing Parameters tcyc toh tohz tac toh tch tcl tsi thi A C Timing Parameters ac_tim td CLK Inputs outputs ...

Page 215: ...4170 login as guest password is your email address IBIS related files are in the directory pub ibis and its sub directories To get documents by email send an email message to archive vhdl org with the following commands in the message body path your_email_address send docs name_of_document For direct modem access dial up to the vhdl org system at 408 945 4170 You can use any baud rate up to 14 400...

Page 216: ...PC SGRAM Specification 26 Revision 0 9 ...

Page 217: ...SO DIMM Module Unbuffered SDRAM SGRAM Graphics 64 bit Non ECC Parity 144 pin Module Revision 0 91 February 1998 Order Number Not Applicable ...

Page 218: ...OUT OF ANY PROPOSAL SPECIFICATION OR SAMPLE Intel disclaims all liability including liability for infringement of any proprietary rights relating to use of information in this specification No license express or implied by estoppel or otherwise to any intellectual property rights is granted herein Copyright Intel Corporation 1996 1997 Third party brands and names are the property of their respecti...

Page 219: ...3 2 CAS Latency 11 6 4 Serial Presence Detect EEPROM 11 7 0 Electrical Characteristics 12 7 1 15 nS Timing 12 7 2 12 nS Timing 12 7 3 10 nS Timing 13 7 4 8 nS Timing 13 7 5 A C Timing Diagrams 14 8 0 PCB Layout Considerations 16 8 1 Clock Routing and Chip Selects 17 8 2 Address Control Routing 18 8 3 Data Routing 19 9 0 Electrical Specifications 21 9 1 SDRAM SGRAM Component Absolute Maximum D C Ra...

Page 220: ... 10 Address and Control Routing 18 11 Data Routing 19 12 Silk Screen Primary Side 23 13 Silk Screen Secondary Side 23 14 Primary Side layer 1 24 15 VCC Plane layer 2 24 16 Inner Signal layer 3 25 17 Inner Signal layer 4 25 18 Ground Plane layer 5 26 19 Secondary Side layer 6 26 Tables 1 Environmental Requirements 3 2 SO DIMM Module Pin Assignments 4 3 Address Translation 9 4 Module Baseline Compon...

Page 221: ...efines four module frequencies speeds 66 MHz 15 nS 83 MHz 12 nS 100 MHz 10 nS and 125 MHz 8 nS 1 2 Labeling Four module frequencies are currently defined they are 66 MHz 15 nS 83 MHz 12 nS 100 MHz 10 nS 125 MHz 8 nS For consistency modules should be clearly marked indicating their rated frequency in MHz The speed in nano seconds is optional This label should be consistent with the module speed set...

Page 222: ...hanical specifications of SO DIMM modules refer to the JEDEC Committee Ballot JC 42 5 95 171 144 pin SDRAM SO DIMM Item 708 4 herein referred to as the JEDEC SO DIMM specification The key position has been shifted to prevent this module from being inserted into a typical main memory SDRAM socket Figure 1 SDRAM SO DIMM Module A000 vsd 100 pin PQFP or TQFP S P D 100 pin PQFP or TQFP Pin 50 ...

Page 223: ...e 1 Environmental Requirements Operating Temperature 0oC to 65oC Operating Humidity 10 to 90 relative humidity noncondensing Operating Pressure 10 106 PSI up to 10 000 ft Storage Temperature 40oC to 70oC Storage Humidity 5 to 95 without condensation Storage Pressure 1 682 PSI up to 50 000 ft at 50oC ...

Page 224: ...Vcc 94 Vcc 23 DQMB7 24 DQMB6 95 DQ31 96 DQ30 25 DQMB5 26 DQMB4 97 DQ29 98 DQ28 27 Vcc 28 Vcc 99 DQ27 100 DQ26 29 DQ47 30 DQ46 101 DQ25 102 DQ24 31 DQ45 32 DQ44 103 Vss 104 Vss 33 DQ43 34 DQ42 105 DQ23 106 DQ22 35 DQ41 36 DQ40 107 DQ21 108 DQ20 37 Vss 38 Vss 109 DQ19 110 DQ18 39 DQ39 40 DQ38 111 DQ17 112 DQ16 41 DQ37 42 DQ36 113 Vcc 114 Vcc 43 DQ35 44 DQ34 115 DQMB3 116 DQMB2 45 DQ33 46 DQ32 117 DQ...

Page 225: ...e followed for connecting 256Kx32 and 512Kx32 devices Figure 2 256K 512 x 64 SGRAM SO DIMM Block Diagram 1 bank of two 256K 512K x 32 DQM0 DQ 7 0 DQM1 DQ 15 8 DQM2 DQ 23 16 DQM3 DQ 31 24 512Kx32 Or 256Kx32 SGRAM D0 CS CS0 DQM4 DQ 39 32 DQM5 DQ 47 40 DQM6 DQ 55 48 DQM7 DQ 63 56 512Kx32 Or 256Kx32 SGRAM D1 CS SCL VSS SBA A2 A1 A0 CLK0 D0 D1 Serial PD optional SDA CKE D0 to D1 D0 to D1 RAS CAS D0 to ...

Page 226: ...QM5 DQ 47 40 DQM6 DQ 55 48 DQM7 DQ 63 56 512Kx32 Or 256Kx32 SGRAM D1 CS SCL VSS SBA A2 A1 A0 CLK0 D0 D1 Serial PD optional SDA CKE D0 to D3 D0 to D3 RAS CAS D0 to D3 D0 to D3 WE DSF D0 to D3 D0 to D3 A 10 0 VCC VSS D0 to D3 D0 to D3 Three bypass capacitors per SGRAM device refer to component section A002 vsd 512Kx32 Or 256Kx32 SGRAM D0 CS 512Kx32 Or 256Kx32 SGRAM D2 CS 512Kx32 Or 256Kx32 SGRAM D3 ...

Page 227: ...iagram 1 bank of one 256K 512K x 32 DQM0 DQ 7 0 DQM1 DQ 15 8 DQM2 DQ 23 16 DQM3 DQ 31 24 512Kx32 Or 256Kx32 SGRAM D0 CS CS0 SCL VSS SBA A2 A1 A0 CLK0 D0 Serial PD optional SDA CKE D0 D0 RAS CAS D0 D0 WE DSF D0 D0 A 10 0 VCC VSS D0 D0 Three bypass capacitors per SGRAM device refer to component section A003 vsd ...

Page 228: ...7 0 DQM1 DQ 15 8 DQM2 DQ 23 16 DQM3 DQ 31 24 CS0 SCL VSS SBA A2 A1 A0 CLK0 D0 D1 Serial PD optional SDA CKE D0 to D1 D0 to D1 RAS CAS D0 to D1 D0 to D1 WE DSF D0 to D1 D0 to D1 A 10 0 VCC VSS D0 to D1 D0 to D1 Three bypass capacitors per SGRAM device refer to component section A004 vsd 512Kx32 Or 256Kx32 SGRAM D0 CS 512Kx32 Or 256Kx32 SGRAM D1 CS CS1 ...

Page 229: ...A8 BA of 256Kx32 device and is connected to pin 51 labeled as A9 AP of 512Kx32 device 6 1 Configuration Graphic controllers can determine the module capabilities one of three ways they are Using the default parameters with power up testing Using resistor strapping options on the data lines Using an optional Serial Presence Detect EEPROM Modules are required to include resistor support 3 resistors ...

Page 230: ...gh Time 5 0 nS Rated 1 4V Clock Low Time 5 0 nS DQM CS Input Setup Time 3 0 nS Other Input Setup Time 3 0 nS DQM CS Input Hold Time 1 0 nS Other Input Hold Time 1 0 nS Output Valid from Clock 11 0 nS Rated 30pf Output Hold from Clock 2 5 nS Rated 30pf CAS Latency 2 2 Tclk CAS to CAS Delay 1 Tclk CAS Bank Delay 1 Tclk CKE to Clock Disable 1 1 Tclk RAS Precharge Time 3 Tclk RAS Active Time 4 Tclk Ac...

Page 231: ...pecified operating environment 6 3 1 Clock Frequency and Memory Timing 6 3 2 CAS Latency A logic low 0 indicates that the resistor strapping is tied to ground Vss A logic high 1 indicates that the resistor strapping is tied to Vcc Resistors should be a 4 7 Kohm resistor on the DQ lines 6 4 Serial Presence Detect EEPROM This EEPROM is optional on the module For additional information refer to the I...

Page 232: ...ical graphic system using an early late memory clock 7 1 15 nS Timing 7 2 12 nS Timing Parameter Symbol Min Max Unit Clock Cycle Time Tcyc 15 0 nS Early Late Clock Tcsk 0 35 1 6 nS Output Valid from Clock Tac 11 0 nS Output Hold from Clock Toh 2 5 nS Input Setup Time Tsi 3 0 nS Input Hold Time Thi 1 0 nS Motherboard Clock Flight Time Tcfm 0 0 3 nS Motherboard Addr Data Cntrl Flight Time Txfm 0 0 3...

Page 233: ...oard Addr Data Cntrl Flight Time Txfm 0 0 3 nS Module Clock Flight Time Tcfs 0 175 0 325 nS Module Flight Addr Data Cntrl Flight Time Txfs 0 0 375 nS Parameter Symbol Min Max Unit Clock Cycle Time Tcyc 8 0 nS Early Late Clock Tcsk 1 3 1 8 nS Output Valid from Clock Tac 6 0 nS Output Hold from Clock Toh 2 5 nS Input Setup Time Tsi 2 0 nS Input Hold Time Thi 1 0 nS Motherboard Clock Flight Time Tcfm...

Page 234: ...rameters Figure 7 Data Write A C Timing Parameters CLK to Gfx Ctrl Addr Ctrl Addr Ctrl Output Addr Ctrl at SO DIMM Interface Addr Ctrl Input A005 vsd CLK to Memory tac txfm tcyc tcsk txfs thi tsi toh CLK to Gfx Ctrl Data Data Output Data at SO DIMM Interface Data Input A006 vsd CLK to Memory tac txfm tcyc tcsk txfs thi tsi toh ...

Page 235: ...5 SO DIMM Module Unbuffered SDRAM SGRAM Graphics Figure 8 Data Read A C Timing Paramters CLK to Gfx Ctrl Data Data Output Data at SO DIMM Interface Data Input A007 vsd CLK to Memory tac txfm tcyc tcsk txfs thi tsi toh ...

Page 236: ...PCB layout considerations for the SO DIMM module Each section looks at three separate topologies one for clocks one for control address and one for data The assumed loading for this configuration is Table 5 Signal Loading Signal 32 bit 64 bit Single sided Double sided Single sided Double sided clocks 1 load 1 load 2 loads 2 loads address control 1 load 2 loads 2 loads 4 loads data 1 load 2 loads 1...

Page 237: ...hs for the clock and chip select routing Figure 9 T Topology Clock Routing A008 vsd b c a o o Table 6 Stub Lengths Clock and Chip Select Routing SDRAM SGRAM Clock Frequency Parameters 15 nS 12 nS 10 nS 8 nS Units Min Max Min Max Min Max Min Max a 75 150 75 150 75 150 75 150 pS b 0 115 0 115 0 115 0 115 pS c 0 115 0 115 0 115 0 115 pS b c 0 225 0 225 0 225 0 225 pS Total Length clock 100 365 175 32...

Page 238: ...ax Min Max Min Max Min Max a 0 37 0 37 0 37 0 37 pS b 0 190 0 190 0 190 0 190 pS c 0 115 0 115 0 115 0 115 pS d 0 115 0 115 0 115 0 115 pS e 0 115 0 115 0 115 0 115 pS f 0 115 0 115 0 115 0 115 pS g 0 115 0 115 0 115 0 115 pS h 0 115 0 115 0 115 0 115 pS b c 75 75 75 75 75 75 75 75 pS b d 75 75 75 75 75 75 75 75 pS c e 0 190 0 190 0 190 0 190 pS c f 0 190 0 190 0 190 0 190 pS d g 0 190 0 190 0 190...

Page 239: ...r the data line routing Figure 11 Data Routing A010 vsd a o Bank 0 d c A B S C D b o Bank 1 Table 8 Byte Ordering Module Byte Front Side Memory Byte Back Side Memory Byte n value BYTE 0 Memory B BYTE 0 Memory D BYTE 3 n 115 pS BYTE 1 Memory B BYTE 3 Memory D BYTE 0 n 35 pS BYTE 2 Memory B BYTE 1 Memory D BYTE 2 n 35 pS BYTE 3 Memory B BYTE 2 Memory D BYTE 1 n 115 pS BYTE 4 Memory A BYTE 1 Memory C...

Page 240: ...Q31 and is optional Table 9 Stub Lengths Data Line Routing SDRAM SGRAM Clock Frequency Parameters 15 nS 12 nS 10 nS 8 nS Units Min Max Min Max Min Max Min Max a n n 75 n n 75 n n 75 n n 75 pS b 0 75 0 75 0 75 0 75 pS c 0 75 0 75 0 75 0 75 pS d 0 125 0 125 0 125 0 125 pS total length 0 n 150 0 n 150 0 n 150 0 n 150 pS ...

Page 241: ...ndershoot voltage duration is 5ns with no input clamp diodes Table 10 Absolute Maximum Ratings Symbol Parameter Min Max Units Vin Vout Voltage on any pin w r t VSS 0 5 VCC 0 5 V VCC VCCQ Voltage Supply pins w r t VSS 0 5 4 5 V Ts Storage Temperature 55 125 C PD Power Dissipation 1 W Table 11 D C Operating Requirements Symbol Parameter Condition Min Max Units Notes VCC Supply Voltage 3 0 3 6 V VCCQ...

Page 242: ...ics 22 Revision 0 91 9 4 Memory Timing Individual DRAM component devices are required to follow the AC timings specified in the Intel PC SGRAM specification Devices which can not meet the minimum timing set forth must program a lower clock speed ...

Page 243: ...DIMM Module Unbuffered SDRAM SGRAM Graphics Appendix A PCB Layout This section show an example of a PQFP TQFP SO DIMM module routed as a six layer PCB Figure 12 Silk Screen Primary Side Figure 13 Silk Screen Secondary Side ...

Page 244: ...SO DIMM Module Unbuffered SDRAM SGRAM Graphics 24 Revision 0 91 Figure 14 Primary Side layer 1 Figure 15 VCC Plane layer 2 ...

Page 245: ...Revision 0 91 25 SO DIMM Module Unbuffered SDRAM SGRAM Graphics Figure 16 Inner Signal layer 3 Figure 17 Inner Signal layer 4 ...

Page 246: ...SO DIMM Module Unbuffered SDRAM SGRAM Graphics 26 Revision 0 91 Figure 18 Ground Plane layer 5 Figure 19 Secondary Side layer 6 ...

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