Intel 740, Design Manual

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Addin Card Design
2-22 Intel740™ Graphics Accelerator Design Guide
Voltage Regulator (Schematic Page 5)
This page shows the circuitry to convert from 3.3 Volts to 2.7 Volts. The regulator used in the
reference design does not need any heat sink for the FET. As shown, the FET will be dissipating
slightly over 1 watt. If a different voltage regulator solution will be used, calculations will be
needed to determine the need for a heatsink. Resistors R50, R44, R42, and R43 are only for the
reference card design. These resistors allow different voltage combinations for core and internal
Intel740 graphics accelerator PLLs. The table at the top of the page describes the voltage
configurations. Core decoupling is shown at the bottom of the page and should be placed close to
the Intel740 graphics accelerator.
Bt829B (Schematic Page 6)
The Bt829B component contains analog inputs which require special routing requirements detailed
in
Section 2.2.5, “Bt829 Video Decoder” on page 2-11 . If these analog inputs are not used, then
they should be tied to ground as is MUX3 in the reference design. The I2CCS pin is pulled low in
the reference design to select an I
2
C address of 88h and 89h. This selection becomes important if
connecting other I
2
C devices like the Bt869.
Note: Care must be taken to ensure that no two devices use the same address.
The QCLK output of the Bt829B obviates the need for connection to the VRDY input on the
Intel740 graphics accelerator as this clock “ANDs” the ACTIVE and CLK outputs of the Bt829B
together. The reference design is designed to support NTSC, PAL and SECAM. If only NTSC is
desired, the circuitry including Y1 can be removed and XT1I should be tied high or low with
XT1O left floating. If only PAL mode of operation is desired, XT1I should be tied high or low with
XT1O floating and Y2 should be replaced with Y1. Decoupling for the component is shown at the
bottom of the page.
Bt869 (Schematic Page 7)
The Bt869 power supply is generated from the VCC3 supply. Decoupling for this supply is shown
at the top of the page. The component contains a 24-bit data port. The Intel740 graphics accelerator
connects only to 12 of these bits. The functionality of this interface is described in the Intel740
Graphics Accelerator Datasheet. The slave input is tied to ground to place this chip in master mode.
If the digital port were to be used as a VMI port, the component should be placed in slave mode.
This page contains the only jumper in the design. This jumper selects which mode (PAL or NTSC)
the Bt869 will operate in. The PC ’98 specification recommends this jumper for designs where a
TV may be the only output display. The ALTADDR pin is pulled high so that the device responds
to an address of 8Ah. This address keeps this device from conflicting with the Bt829B’s I
2
C
address. Note that ROMA17 is wired to the CLKI pin while ROMA14 is connected to the CLKO
pin. ROMA17 is also called CLKOUT and ROMA14 is called CLKIN. The Intel740’s graphics
accelerator CLKOUT pin corresponds to the Bt869’s CLKI pin while the CLKIN pin corresponds
to the CLKO pin on the Bt869. The DAC lines have special routing requirements detailed in
section. These DAC lines allow the component to output S-Video and composite video.
VMI Video Connectors (Schematic Page 8)
The VMI video connectors are used for the attachment of a DVD daughter card or video capture
card. The capture port is connected to the 26 pin header while the bi-directional host port is
connected to the 40 pin header. The reference design uses a 2A fuse for the 3.3 volt supply to the
40 pin header. The 2A fuse is allowed for the 5 volt supply and 1A is allowed for the 12 volt
supply. GPIO5 and GPIO7 come to the header for added DVD daughter card functionality control.
GPIO8 is used for power down operation on the card. The I
2
C connections on the 26 pin header are
3.3 volt signals. Mechanical dimensions for the placement of the connectors is shown in
Section 5.3, “VMI Header Placement” on page 5-2 .