Intel 6 SERIES, User Manual

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About This Document
2 nd Generation Intel ® Core™ Processor with Intel ® 6 Series Chipset Development Kit
User Guide March 2011
4 Document Number: 325208-001
3.2.7.3 Switchable Graphics ................................................................... 37
3.2.8 USB Connectors ........................................................................................ 38
3.2.8.1 USB2.0 ..................................................................................... 38
3.2.9 LPC Super I/O (SIO)/LPC Slot ..................................................................... 40
3.2.10 Serial Port, IrDA ........................................................................................ 40
3.2.11 System Management Controller (SMC)/Keyboard Controller (KBC).................. 40
3.2.12 SPI .......................................................................................................... 41
3.2.12.1 Multi-BIOS Support .................................................................... 41
3.2.12.2 Clocks ...................................................................................... 42
3.2.12.3 CPU_ITP Clock and XDP Clock ..................................................... 43
3.2.13 Real Time Clock ........................................................................................ 44
3.3 Debug Interfaces .................................................................................................. 45
3.3.1 Processor and PCH Debug .......................................................................... 45
3.4 Chassis ................................................................................................................ 45
3.5 Power Supply Solutions, Usage, and Recommendations ............................................ 45
3.5.1 Power Supply Solutions .............................................................................. 45
3.5.2 Power Supply Usage and Recommendation .................................................. 46
3.6 Power Management .............................................................................................. 47
3.6.1 Power Management States ......................................................................... 47
4 Development Board Summary .................................................................................... 48
4.1 Features .............................................................................................................. 48
4.2 Connectors .......................................................................................................... 51
4.2.1 Back Panel Connectors ............................................................................... 51
4.3 Configuration Settings ........................................................................................... 52
4.3.1 Configuration Jumpers/Switches ................................................................. 52
4.4 Power On and Reset Button ................................................................................... 53
4.5 LEDs ................................................................................................................... 54
5 Quick Start ................................................................................................................. 56
5.1 Required Peripherals ............................................................................................. 56
5.2 Instructions to Flash BIOS to SPI ........................................................................... 56
5.3 H8 Programming .................................................................................................. 56
5.4 Key Jumpers ........................................................................................................ 57
Figures
Figure 1. Development Board Block Diagram ........................................................ 22
Figure 2. Side View of Stacked SODIMM Slots ....................................................... 27
Figure 3. PCIe* Port Mapping – Schematic Snapshot ............................................. 31
Figure 4. On-Board LAN Block Diagram ................................................................ 33
Figure 5. Back Panel Connectors .......................................................................... 35
Figure 6. Display Ports On-Board ......................................................................... 36
Figure 7 Mini PCIe Connector Soldered In Place of DMC ......................................... 37
Figure 8. Switchable Graphics with eDP from PCH ................................................. 38
Figure 9. Clock (Integrated Mode) Block Diagram .................................................. 43
Figure 10. Block Diagram of GDXC and XDP Clock on the Development Board .......... 43
Figure 11. Layout Snapshot for Reworks for GDXC and XDP Clock Options On-Board 44
Figure 12. Development Board Components – Top View ......................................... 48
Figure 13. Development Board Components - Bottom View .................................... 50
Figure 14. Back Panel Connectors ........................................................................ 51
Figure 15. Jumpers for Programming SPI and H8 .................................................. 58