Development Kit Features
2
nd
Generation Intel
®
Core™ Processor with Intel
®
6 Series Chipset Development Kit
March 2011
User Guide
Document Number: 325208-001
27
Figure 2. Side View of Stacked SODIMM Slots
NOTE:
The channel B connector has a height of 5.2 mm and the Channel A slot has height of
9.2 mm.
3.1.5
Graphics Support
3.1.5.1
Internal Graphics Support
The development board supports internal graphics (from CPU) through Embedded
display port from the processor. There are x4 differential lanes from processor to
panel (sink). The processor can support link rates of 1.62 Gbps or 2.7 Gbps.
The eDP is no longer mux’ed with PEG lanes; the processor has dedicated eDP ports
and an on-board eDP connector is provided to support this feature. The Eaglemont
AIC is not required to support eDP from the processor.
To enable eDP:
J8D3 should be (1-2). This is done because the eDP and LVDS embedded displays
have the same enable/control signals. To ensure that only one embedded display is
supported at a time, eDP should be enabled and disable LVDS display. By doing the
jumper settings change, power supply input to eDP panel is enabled and the LVDS is
disabled. This jumper is a new addition for the easy switching between LVDS and eDP
display.
By default on-board configuration is J8D3 (2-3), i.e., this supports LVDS panel.
Jumper setting change is required to enable eDP panel only.
Pull-down CFG4 strap by shorting the jumper J1E1. Strap definition is provided in the
following table.