Development Kit Features
2
nd
Generation Intel
®
Core™ Processor with Intel
®
6 Series Chipset Development Kit
March 2011
User Guide
Document Number: 325208-001
25
3.1.1
Clock Requirements
The processor requires two external clock inputs:
•
100 MHz BCLK given as reference clock input to Core, DMI, Intel FDI, PEG and
DDR PLLs.
•
120 MHz DP_CLK given as reference CLK input for the Display port PLL
Note:
To achieve a 100 MHz BCLK, ensure the J6G1 jumper on-board is unstuffed (1-X).
3.1.2
Processor Voltage Regulator
The board implements an on-board Intel Mobile Voltage Positioning (Intel
®
MVP)-7
voltage regulator (VR) for the processor-core and graphics-core power supply.
The main feature of Intel MVP-7 regulator is that it is serial-VID-based, which is
introduced for the first time in this platform. Both the processor core and graphics
core VRs are integrated into single package. The serial VID interface is shared by both
the processor core and graphics core VRs.
3.1.2.1
SVID Supported in Intel
®
MVP-7 Voltage Regulator
Intel
®
Mobile Voltage Positioning (Intel
®
MVP)-7 uses a 3-wire serial interface called
SVID (DATA, CLK and ALERT#), for regulating both the processor core and graphics
core voltages.
Some of the main differences in the platform with the introduction of SVID are:
•
SVID can be used to communicate the power states along with the VID signals.
Hence, signals like PSI# and DPRSLPVR used to indicate the power states in
previous platforms, will be absent in this platform.
•
There is no support for on-board override mechanism as done in case of Parallel
VIDs in previous platforms.
•
SVID interface is shared by both the processor core VR and graphics core VR.
Note:
Ensure jumpers J1C6, J1D3 and J1D7, which are placed on the SVID path between
processor and Intel MVP, are shorted (1-2).
3.1.3
Power Management and Key Signals
The processor supports C0, C2, C2E, C3, Deep Power Down Technology, and C7
states. All power management handshakes happen over the DMI-2 interface. None of
the ‘Power State’ status signals can be observed on the board directly. The only way
to detect the entry to/exit from the C2/C3 C-States is to read the DMI-2
transmissions.
Some important power management pins on the processor are listed below.
•
SM_DRAMPWROK: Input from the Intel
®
6 Series Chipset PCH indicating to the
MCH with regards to DRAM power. When DRAM power is turned off, MCH uses this
as one of the conditions to assert DDR3 RST signal.
