Intel 520J - Pentium 4 2.80GHz 800MHz 1MB Socket 775 CPU Datasheet Download Page 43

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Datasheet

Land Listing and Signal Descriptions

Land Listing and Signal
Descriptions

This chapter provides the processor land assignment and signal descriptions.

4.1

Processor Land Assignments

This section contains the land listings for the Pentium 4 processor in the 775-land package. The
landout footprint is shown in

Figure 4-1

and

Figure 4-2

. These figures represent the landout

arranged by land number and they show the physical location of each signal on the package land
array (top view).

Table 4-1

is a listing of all processor lands ordered alphabetically by land (signal)

name.

Table 4-2

is also a listing of all processor lands; the ordering is by land number.

Summary of Contents for 520J - Pentium 4 2.80GHz 800MHz 1MB Socket 775 CPU

Page 1: ...70 571 560 561 550 551 540 541 530 531 and 520 521 Supporting Hyper Threading Technology1 Datasheet On 90 nm Process in 775 land LGA Package and supporting Intel Extended Memory 64 Technology May 2005...

Page 2: ...processor family not across different processor families 1 Hyper Threading Technology requires a computer system with an Intel Pentium 4 processor supporting Hyper Threading Technology and an HT Techn...

Page 3: ...24 2 11 Processor DC Specifications 24 2 12 VCC Overshoot Specification 33 2 12 1 Die Voltage Validation 33 2 13 GTL FSB Specifications 34 3 Package Mechanical Specifications 35 3 1 Package Mechanica...

Page 4: ...ates 86 6 2 3 Stop Grant State 87 6 2 4 Enhanced HALT Snoop or HALT Snoop State Grant Snoop State 88 7 Boxed Processor Specifications 89 7 1 Mechanical Specifications 90 7 1 1 Boxed Processor Cooling...

Page 5: ...t Side 45 5 1 Thermal Profile for Processors with PRB 1 77 5 2 Thermal Profile for Processors with PRB 0 78 5 3 Case Temperature TC Measurement Location 79 5 4 Thermal Monitor 2 Frequency and Voltage...

Page 6: ...ations 31 2 13PWRGOOD and TAP Signal Group DC Specifications 32 2 14VTTPWRGD DC Specifications 32 2 15BSEL 2 0 and VID 5 0 DC Specifications 32 2 16BOOTSELECT DC Specifications 32 2 17VCC Overshoot Sp...

Page 7: ...Added Icc Enhanced Auto Halt specifications Added support for Thermal Monitor 2 September 2004 003 Added specifications for processor number 570 with PRB 1 November 2004 004 Added specifications for p...

Page 8: ...8 Datasheet Contents...

Page 9: ...r Threading Technology1 HT Technology for all frequencies with 800 MHz front side bus FSB Intel Pentium 4 processors 571 561 551 541 531 and 521 support Intel Extended Memory 64 Technology EM64T Suppo...

Page 10: ...10 Datasheet Contents...

Page 11: ...el Pentium 4 processor 571 561 541 531 and 521 support Intel Extended Memory 64 Technology EM64T as an enhancement to Intel s IA 32 architecture This enhancement enables the processor to execute opera...

Page 12: ...nals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex...

Page 13: ...al and concepts available in the following documents may be beneficial when reading this document Table 1 1 References Document Document Numbers Location Intel Pentium 4 Processor on 90 nm Process Spe...

Page 14: ...14 Datasheet Introduction...

Page 15: ...d must be terminated on the system board See Table 2 4 for details regarding these signals The GTL bus depends on incident wave switching Therefore timing calculations for GTL signals are based on fli...

Page 16: ...ctly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the Pentium 4 processor in the 775 land package core frequency is a multiple o...

Page 17: ...the voltage level corresponding to the state of VID 5 0 A 1 in this table refers to a high voltage level and a 0 refers to low voltage level If the processor socket is empty VID 5 0 x11111 or the volt...

Page 18: ...1 0 1 0 0 1 3500 0 0 0 1 0 0 0 9875 0 1 0 1 0 0 1 3625 1 0 0 0 1 1 1 0000 1 1 0 0 1 1 1 3750 0 0 0 0 1 1 1 0125 0 1 0 0 1 1 1 3875 1 0 0 0 1 0 1 0250 1 1 0 0 1 0 1 4000 0 0 0 0 1 0 1 0375 0 1 0 0 1 0...

Page 19: ...ese supplies must be low pass filtered from VTT The AC low pass requirements with input at VTT are as follows 0 2 dB gain in pass band 0 5 dB attenuation in pass band 1 Hz 34 dB attenuation from 1 MHz...

Page 20: ...round a resistor will also allow for system testability For unused GTL input or I O signals use pull up resistors of the same value as the on die termination resistors RTT Refer to Table 2 18 for more...

Page 21: ...e common clock source synchronous and asynchronous Table 2 3 FSB Signal Groups Signal Group Type Signals1 GTL Common Clock Input Synchronous to BCLK 1 0 BPRI DEFER RS 2 0 RSP TRDY GTL Common Clock I O...

Page 22: ...onal timing requirements for entering and leaving the low power states Table 2 4 Signal Characteristics Signals with RTT Signals with no RTT A 35 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BOOTSELECT1 BPRI D 63...

Page 23: ...quency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 2 6 defines the possible combinations of the signals and the frequency...

Page 24: ...the processor FSB are in the GTL signal group The DC specifications for these signals are listed in Table 2 12 Previously legacy signals and Test Access Port TAP signals to the processor used low vol...

Page 25: ...C for processor with multiple VID 3 80 GHZ PRB 1 3 60 GHz PRB 1 3 40 GHz PRB 1 3 40 GHz PRB 0 3 20 GHz PRB 0 3 GHz PRB 0 2 80 GHz PRB 0 119 119 119 78 78 78 78 A 9 ISGNT 570 571 560 561 550 550 551 54...

Page 26: ...b jected to any Vcc and Icc combination wherein VCC exceeds Vcc_max for a given current 6 775_VR_CONFIG_04A and 775_VR_CONFIG_04B refer to voltage regulator configurations that are defined in the Volt...

Page 27: ...ust be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for socket loadline guide lines and VR implementation details 4 Adhere...

Page 28: ...k for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and V...

Page 29: ...10 1 Design Guide For Desktop LGA775 Socket for socket loadline guide lines and VR implementation details 4 Adherence to this loadline specification for the processor is required to ensure reliable pr...

Page 30: ...its must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Down VRD 10 1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details 4 Ad...

Page 31: ...Low Current VTT 0 50 RTT_MIN RON_MIN A 8 8 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load ILI Input Leakage Current N...

Page 32: ...nd is not specified into the test load ILI Input Leakage Current 200 A 6 6 Leakage to VSS with land held at VTT ILO Output Leakage Current 200 A RON Buffer On Resistance 7 12 Table 2 14 VTTPWRGD DC Sp...

Page 33: ...ove VID 2 12 1 Die Voltage Validation Overshoot events from application testing on real processors must meet the specifications in Table 2 17 when measured across the VCC_SENSE and VSS_SENSE lands Ove...

Page 34: ...1 02 0 67 VTT V 2 3 4 5 2 The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of VTT 3 GTLREF...

Page 35: ...er IHS Thermal Interface Material TIM Processor core die Package substrate Capacitors NOTE 1 Socket and motherboard are included for reference and are not part of processor package 3 1 Package Mechani...

Page 36: ...36 Datasheet Package Mechanical Specifications Figure 3 2 Processor Package Drawing 1...

Page 37: ...Datasheet 37 Package Mechanical Specifications Figure 3 3 Processor Package Drawing 2...

Page 38: ...38 Datasheet Package Mechanical Specifications Figure 3 4 Processor Package Drawing 3...

Page 39: ...ximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Table 3 1 Processor Loading Specifications Parameter Minimum Ma...

Page 40: ...the package 3 7 Processor Materials Table 3 3 lists some of the package components and associated materials 3 8 Processor Markings Figure 3 5 and Figure 3 6 show the topside markings on the processor...

Page 41: ...nates are referred to throughout the document to identify processor lands Figure 3 6 Processor Top Side Marking Example for Processors Supporting Intel EM64T ATPO S N ProcessorNumber S Spec CountryofA...

Page 42: ...22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 2 3 4 5 6 7...

Page 43: ...ngs for the Pentium 4 processor in the 775 land package The landout footprint is shown in Figure 4 1 and Figure 4 2 These figures represent the landout arranged by land number and they show the physic...

Page 44: ...VCC VCC VCC VCC VCC VCC VCC VCC W VCC VCC VCC VCC VCC VCC VCC VCC V VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS V...

Page 45: ...VSS A23 A21 VSS LL_ID1 VTT_OUT_ RIGHT AA VCC VSS A19 VSS A20 RSVD VSS BOOT SELECT Y VCC VSS A18 A16 VSS TESTHI1 TESTHI12 MSID0 W VCC VSS VSS A14 A15 VSS LL_ID0 MSID1 V VCC VSS A10 A12 A13 AP1 AP0 VSS...

Page 46: ...nput Output ADSTB1 AD5 Source Synch Input Output AP0 U2 Common Clock Input Output AP1 U3 Common Clock Input Output BCLK0 F28 Clock Input BCLK1 G28 Clock Input BINIT AD3 Common Clock Input Output BNR C...

Page 47: ...19 Source Synch Input Output D61 A19 Source Synch Input Output D62 A22 Source Synch Input Output Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction D63 B22 Source Sync...

Page 48: ...and Signal Buffer Type Direction RESERVED Y3 RESERVED D23 RESERVED AK6 RESERVED G6 RESET G23 Common Clock Input RS0 B3 Common Clock Input RS1 F5 Common Clock Input RS2 A3 Common Clock Input RSP H4 Com...

Page 49: ...VCC AG15 Power Other VCC AG18 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AG19 Power Other VCC AG21 Power Other VCC AG22 Power Other VCC AG25 Po...

Page 50: ...Power Other VCC AM9 Power Other VCC AN11 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AN12 Power Other VCC AN14 Power Other VCC AN15 Power Other...

Page 51: ...e 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC U30 Power Other VCC U8 Power Other VCC V8 Power Other VCC W23 Power Other VCC W24 Power Other VCC W25 Power Other VC...

Page 52: ...SS AE5 Power Other VSS AE7 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AF10 Power Other VSS AF13 Power Other VSS AF16 Power Other VSS AF17 Power...

Page 53: ...7 Power Other VSS AM20 Power Other VSS AM23 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AM24 Power Other VSS AM27 Power Other VSS AM28 Power Oth...

Page 54: ...Other VSS H7 Power Other VSS H8 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS H9 Power Other VSS J4 Power Other VSS J7 Power Other VSS K2 Power O...

Page 55: ...23 Power Other VTT A25 Power Other VTT A26 Power Other VTT A27 Power Other VTT A28 Power Other VTT A29 Power Other VTT A30 Power Other VTT B25 Power Other VTT B26 Power Other VTT B27 Power Other VTT B...

Page 56: ...0 Source Synch Input Output B10 D10 Source Synch Input Output B11 VSS Power Other B12 D13 Source Synch Input Output B13 RESERVED B14 VSS Power Other B15 D53 Source Synch Input Output B16 D55 Source Sy...

Page 57: ...2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction E6 RESERVED E7 RESERVED E8 VSS Power Other E9 D19 Source Synch Input Output E10 D21 Source Synch Input Output E11 VSS Power Othe...

Page 58: ...TESTHI5 Power Other Input G27 TESTHI4 Power Other Input G28 BCLK1 Clock Input G29 BSEL0 Power Other Output G30 BSEL2 Power Other Output H1 GTLREF Power Other Input Table 4 2 Numerical Land Assignment...

Page 59: ...L5 A3 Source Synch Input Output L6 VSS Power Other L7 VSS Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction L8 VCC Power Other L23 VSS Power Other L24 VSS Po...

Page 60: ...Power Other T23 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction T24 VCC Power Other T25 VCC Power Other T26 VCC Power Other T27 VCC Power Other T28 VCC...

Page 61: ...er AA26 VSS Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AA27 VSS Power Other AA28 VSS Power Other AA29 VSS Power Other AA30 VSS Power Other AB1 VSS Powe...

Page 62: ...2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AF1 TDO TAP Output AF2 BPM4 Common Clock Input Output AF4 A28 Source Synch Input Output AF5 A27 Source Synch Input Output AF6 VS...

Page 63: ...r AH22 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AH23 VSS Power Other AH24 VSS Power Other AH25 VCC Power Other AH26 VCC Power Other AH27 VCC Powe...

Page 64: ...Other AL13 VSS Power Other AL14 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AL15 VCC Power Other AL16 VSS Power Other AL17 VSS Power Other AL18 VCC...

Page 65: ...VSS Power Other AN11 VCC Power Other AN12 VCC Power Other AN13 VSS Power Other AN14 VCC Power Other AN15 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Directio...

Page 66: ...he TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0...

Page 67: ...counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins lands of all processor FSB agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a...

Page 68: ...r sub phase for that 16 bit group DBR Output DBR Debug Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an...

Page 69: ...ding break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Int...

Page 70: ...interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS program...

Page 71: ...ack any of their contents For a power on Reset RESET must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications On observing active RESET all FSB agents...

Page 72: ...ay occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor...

Page 73: ...ense or measure ground near the silicon with little noise VSS_MB_ REGULATION Output This land is provided as a voltage regulator feedback sense point for VSS It is connected internally in the processo...

Page 74: ...74 Datasheet Land Listing and Signal Descriptions...

Page 75: ...erm reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature TC specificati...

Page 76: ...ecification Table 5 1 Processor Thermal Specifications Processor Number Core Frequency GHz Thermal Design Power W Minimum TC C Maximum TC C Notes 520 521 2 80 PRB 0 84 5 See Table 5 3 and Figure 5 2 1...

Page 77: ...6 68 0 8 46 0 38 53 5 68 61 0 98 68 5 10 46 5 40 54 0 70 61 5 100 69 0 12 47 0 42 54 5 72 62 0 102 69 5 14 47 5 44 55 0 74 62 5 104 70 0 16 48 0 46 55 5 76 63 0 106 70 5 18 48 5 48 56 0 78 63 5 108 71...

Page 78: ...34 53 7 64 62 1 6 45 9 36 54 3 66 62 7 8 46 4 38 54 8 68 63 2 10 47 0 40 55 4 70 63 8 12 47 6 42 56 0 72 64 4 14 48 1 44 56 5 74 64 9 16 48 7 46 57 1 76 65 5 18 49 2 48 57 6 78 66 0 20 49 8 50 58 2 8...

Page 79: ...es the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the...

Page 80: ...adjust its operating frequency bus multiplier and input voltage VID This combination of reduced frequency and VID results in a decrease in processor power consumption A processor enabled for Thermal M...

Page 81: ...775 land package must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the ACPI P_CNT Control Register located in the processor IA32_THERM_CONTROL MSR is wr...

Page 82: ...in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Ther...

Page 83: ...oss the diode k Boltzmann Constant and T absolute temperature Kelvin 5 Devices found to have an ideality factor of 1 0183 to 1 023 will create a temperature error approximately 2 C higher than the act...

Page 84: ...84 Datasheet Thermal Specifications and Design Considerations...

Page 85: ...toHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 6 1 for a visual representation of th...

Page 86: ...are Developer s Manual Volume III System Programmer s Guide for more information The system can generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPC...

Page 87: ...sertion of the STPCLK signal A transition to the HALT Grant Snoop state will occur when the processor detects a snoop on the FSB see Section 6 2 3 While in the Stop Grant State SMI INIT BINIT and LINT...

Page 88: ...a snoop transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the...

Page 89: ...ll figures in this chapter are dimensioned in millimeters and inches in brackets Figure 7 1 shows a mechanical representation of a boxed Pentium 4 processor in the 775 land package Note Drawings in th...

Page 90: ...nts and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 7 2 side view and Figure 7 3 top view The airspace requirements for the boxed processor fan heatsink must als...

Page 91: ...sembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly 7 2 Electrical Requirements 7 2 1 Fan Heatsink Power Supply...

Page 92: ...or on the system board itself Figure 7 6 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 110 mm 4 33 inches from...

Page 93: ...e Table 5 1 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow o...

Page 94: ...4 Datasheet Boxed Processor Specifications Figure 7 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements Top View Figure 7 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements Side Vie...

Page 95: ...reases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Figu...

Page 96: ...t sink solution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard designs Under th...

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