18
Channel
Allocation
Channel ID
Composition
CPU0
Channel A (active)
CPU0_CAD0
Channel A
CPU0_CAD1
Channel B (active)
CPU0_CBD0
Channel B
CPU0_CBD1
Channel C (active)
CPU0_CCD0
Channel C
CPU0_CCD1
Channel D (active)
CPU0_CDD0
Channel D
CPU0_CDD1
Channel E (active)
CPU0_CED0
Channel E
CPU0_CED1
Channel F (active)
CPU0_CFD0
Channel F
CPU0_CFD1
Channel G (active)
CPU0_CGD0
Channel G
CPU0_CGD1
Channel H (active)
CPU0_CHD0
Channel H
CPU0_CHD1
CPU1
Channel A (active)
CPU1_CAD0
Channel A
CPU1_CAD1
Channel B (active)
CPU1_CBD0
Channel B
CPU1_CBD1
Channel C (active)
CPU1_CCD0
Channel C
CPU1_CCD1
Channel D (active)
CPU1_CDD0
Channel D
CPU1_CDD1
Channel E (active)
CPU1_CED0
Channel E
CPU1_CED1
Channel F (active)
CPU1_CFD0
Channel F
CPU1_CFD1
Channel G (active)
CPU1_CGD0
Channel G
CPU1_CGD1
Channel H (active)
CPU1_CHD0
Channel H
CPU1_CHD1
3. DIMM Compatibility
Configure the DDR4 DIMMs by referring to the rules as follows:
The server must use DDR4 DIMMs of the same Part No. (P/N code) with the
operating speed at the lowest value of each item below:
‐
The memory speed supported by a specific CPU.
‐
The maximum working speed of a specific memory configuration.
Mixed use of DDR4 DIMMs is not supported for different types (RDIMM, LRDIMM)
and different specifications (capacity, bit width, rank, height, and so on).
For specific system options, consult your local Inspur sales representative or refer
to