CMOS setup
67
The value in this field depends on write wait state parameters of the installed memory
chips (DRAM).
The Choice: X-2-2-2, X-3-3-3.
!"
Page Mode Read WS
The value in this field depends on read wait state parameters of the installed memory
chips (DRAM).
The Choice: X-4-4-4, X-3-3-3.
!"
RAS Precharge Period
This option allows you to determine the number of CPU clocks allocated for the
ow
ddress
trobe to accumulate its charge before the DRAM is refreshed. If insufficient
time is allowed, refresh may be incomplete and data lost.
The choice: 3T, 4T
!"
RAS-To-CAS Delay Time
This setup item allows you to determine the timing of the transition from Row Address
Strobe (RAS) to Column Address Strobe (CAS).
The Choice: 2T, 3T
!"
EDO Read WS
This sets the timing for burst mode reads from EDO RAM. Burst read requests are
generated by the CPU in four separate parts. The first part provides the location within
the DRAM where the read is to take place while the remaining three parts provide the
actual data. The lower the timing numbers, the faster the system will address memory.
The Choice: X-2-2-2, X-3-3-3.
!"
DRAM Speculative Read
When the ‘Speculative Read’ is enabled, the controller will issue the read command
slightly before it has finished determining the address.
The Choice: Enabled, Disabled.
!"
Pipelined Function
CMOS setup
68
When Enabled, the controller signals the CPU for a new memory address before all
data transfers for the current cycles are complete, resulting in faster performance
The Choice : Enabled, Disabled
!"
DRAM Refresh Period (us)
This sets the number of DRAM allowed be refreshed by chipset.
The Choice :15,30, 60 ,120, 256 (us)
!"
DRAM Data Integrity Mode
Select Parity or ECC (error-correcting code), according to the type of installed DRAM.
The Choice: Disabled, ECC, Parity.
!"
Memory Hole At 15-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached.
The choice : Enabled, Disabled.
!"
Primary Frame Buffer
Select a size for the PCI frame buffer. The size of the buffer should not impinge on
local memory.
The choice : Disabled, 2MB 4MB, 8MB, 16MB.
!"
VGA Frame Buffer
When Enabled, a fixed VGA frame buffer from A000h to BFFFh and a CPU-to-PCI
write buffer are implemented.
The choice: Enabled , Disabled.
!"
Data Merge
This field controls the word-merge feature for frame buffer cycles. When Enabled, this
controller checks the eight CPU Byte Enable signals to determine if data words read
from the PCI bus by the CPU can be merged.
The choice: Enabled , Disabled.
