Infineon TRAVEO T2G family CYT4D Series, Manual, Page: 45 / 80

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Infineon TRAVEO T2G family CYT4D Series Manual Download Page 45

Application Note

45 of 80

002-26071 Rev. *B

2021-09-07

Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs

Configuration of the FLL and PLL

Code Listing 36

Cy_SysClk_PllManualConfigure() function

  }

  if((config->referenceDiv < MIN_REF_DIV) || (MAX_REF_DIV < config->referenceDiv))
  {
return(CY_SYSCLK_BAD_PARAM);
  }

  if((config->feedbackDiv < (config->lfMode ? MIN_FB_DIV_LF : MIN_FB_DIV_NORM)) ||
((config->lfMode ? MAX_FB_DIV_LF : MAX_FB_DIV_NORM) < config->feedbackDiv))
  {
return(CY_SYSCLK_BAD_PARAM);
  }

  un_CLK_PLL_CONFIG_t tempClkPLLConfigReg;
  tempClkPLLConfigReg.u32Register = SRSS->unCLK_PLL_CONFIG[pllNo].u32Register;
  if (tempClkPLLConfigReg.stcField.u1ENABLE != 0ul)

/* 1 = enabled */

  {
  return(CY_SYSCLK_INVALID_STATE);
  }

/* no errors */
/* If output mode is bypass (input routed directly to output), then done.
The output frequency equals the input frequency regardless of the frequency parameters. */

if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)

  {
  tempClkPLLConfigReg.stcField.u7FEEDBACK_DIV = (uint32_t)config->feedbackDiv;
  tempClkPLLConfigReg.stcField.u5REFERENCE_DIV = (uint32_t)config->referenceDiv;
  tempClkPLLConfigReg.stcField.u5OUTPUT_DIV = (uint32_t)config->outputDiv;
  tempClkPLLConfigReg.stcField.u1PLL_LF_MODE = (uint32_t)config->lfMode;
  }
  tempClkPLLConfigReg.stcField.u2BYPASS_SEL = (uint32_t)config->outputMode;

  SRSS->unCLK_PLL_CONFIG[pllNo].u32Register = tempClkPLLConfigReg.u32Register;

  return (CY_SYSCLK_SUCCESS);
}

Code Listing 37

Cy_SysClk_GetPllNo() function

__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_GetPllNo(uint32_t pathNo, uint32_t* pllNo)
{

/* check for error */

if ((pathNo <= SRSS_NUM_PLL400M) || (pathNo > (SRSS_NUM_P SRSS_NUM_PLL)))
{

/* invalid clock path number */

  return(CY_SYSCLK_BAD_PARAM);
  }

  *pllNo = pathNo - (uint32_t)(SRSS_NUM_P 1u);
  return(CY_SYSCLK_SUCCESS);
}

Code Listing 38

Cy_SysClk_PllCalucDividers() function

__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllCalucDividers(uint32_t inFreq,
uint32_t targetOutFreq,
const cy_stc_pll_limitation_t* lim,
uint32_t fracBitNum,
uint32_t* feedBackDiv,
uint32_t* refDiv,
uint32_t* outputDiv,
uint32_t* feedBackFracDiv)
{
  uint64_t errorMin = 0xFFFFFFFFFFFFFFFFull;

  if(feedBackDiv == NULL)
  {
  return (CY_SYSCLK_BAD_PARAM);
  }

  if((feedBackFracDiv == NULL) && (fracBitNum != 0ul))
  {
  return (CY_SYSCLK_BAD_PARAM);
  }

  if(refDiv == NULL)

(9) PLL200 configuration

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Summary of Contents for TRAVEO T2G family CYT4D Series

Page 1: ...EO T2G family CYT4D series MCUs Table of contents About this document 1 Table of contents 1 1 Introduction 3 2 Clock system for TRAVEO T2G family MCUs 4 2 1 Overview of the clock system 4 2 2 Clock resources 4 2 3 Clock system functions 4 2 4 Basic clock system settings 11 3 Configuration of the clock resources 12 3 1 Setting the ECO 12 3 1 1 Use case 13 3 1 2 Configuration 13 3 1 3 Sample code fo...

Page 2: ...gs example of the TCPWM timer 55 5 10 Setting ECO_Prescaler 57 5 10 1 Use case 58 5 10 2 Configuration 58 5 10 3 Sample code for the initial configuration of ECO prescaler settings 59 5 11 Configuring the LPECO_Prescaler 61 5 11 1 Use case 61 5 11 2 Configuration 62 5 11 3 Sample code for the initial configuration of LPECO prescaler settings 62 6 Supplementary information 65 6 1 Input clocks in pe...

Page 3: ...ple high performance analog and digital functions The TRAVEO T2G clock system supports high and low speed clocks using both internal and external clock sources One of the typical use case for clock input is internal real time clock RTC The TRAVEO T2G MCU supports phase locked loop PLL and frequency locked loop FLL to generate clocks that operate the internal circuit at a high speed The TRAVEO T2G ...

Page 4: ...MHz TYP Internal low speed oscillator 0 ILO0 This is a built in clock with a frequency of 32 kHz TYP Internal low speed oscillator 1 ILO1 ILO1 has the same function as ILO0 but ILO1 can monitor the clock of ILO0 External clock sources All these clocks are disabled by default External crystal oscillator ECO This clock uses an external oscillator whose input frequency range is between 3 988 MHz and ...

Page 5: ...CSV CLK_HF7 Predivider 1 2 4 8 CSV CLK_HF8 CLK_PATH9 ECO Prescaler ECO ILO0 ILO1 WCO CSV CLK_REF_HF CSV CSV CLK_LF Active Domain DeepSleep Domain Hibernate Domain REF_MUX PATH_MUX9 DSI_MUX9 ROOT_MUX5 ROOT_MUX6 ROOT_MUX7 ROOT_MUX8 ROOT_MUX4 ROOT_MUX3 ROOT_MUX2 ROOT_MUX1 PATH_MUX8 DSI_MUX8 BYPASS_MUX8 PATH_MUX7 DSI_MUX7 BYPASS_MUX7 PATH_MUX6 DSI_MUX6 BYPASS_MUX6 PATH_MUX5 DSI_MUX5 BYPASS_MUX5 BYPASS...

Page 6: ... CLK_PATHx 0 through 9 are used as the input sources for high frequency clocks CLK_HF CLK_HFx 0 through 13 are recognized as high frequency clocks FLL Generates the high frequency clock PLL Generates the high frequency clock There are two kinds of PLL PLL200 and PLL400 PLL200 is with SSCG and fractional operation and PLL400 is with SSCG and fractional operation BYPASS_MUX Selects the clock to be o...

Page 7: ... 1 256 Event generator SMIF CPUSS fast infrastructure SRSS EFUSE Ethernet CLK_GR4 PERI_GR4_CLOCK_CTLregister INT_DIV bit Divider 1 256 IOSS TCPWM 0 CLK_GR8 PERI_GR8_CLOCK_CTLregister INT_DIV bit Divider 1 256 AUDIOSS CPUSS DEBUG TRC_DBG_CLOCK_CTL register INT_DIV bit Divider 1 256 Peripheral clock divider 0 PERI VIDEOSS Figure 3 Block diagram for CLK_HF0 CLK_MEM Clock input to the CPUSS of the fas...

Page 8: ... Clock divider 8 0 CLK_PERI PERI_DIV_8_CTL register INT8_DIV bit Clock divider 16 0 PERI_DIV_16_CTL register INT16_DIV bit Clock divider 16 5 PERI_DIV_16_5_CTL register FRAC5_DIV bit INT24_DIV bit PERI_CLOCK_CTLregister TYPE_SEL bit DEV_SEL bit 9 dividers 16 dividers 7 dividers 124multiplexers Clock Generation Clock divider 24 5 PERI_DIV_24_5_CTL register FRAC5_DIV bit INT24_DIV bit 3 dividers Clo...

Page 9: ...nd CM7_1 respectively CLK_FAST_0 CLK_HF1 CM7_0 FAST_0_CLOCK_CTL register INT_DIV bit Divider 1 256 CLK_FAST_1 CM7_1 FAST_1_CLOCK_CTL register INT_DIV bit Divider 1 256 Figure 5 Block diagram for the CLK_HF1 Figure 6 shows the distribution of the CLK_HF2 which is a clock source for the CLK_GR and PCLK CLK_GR5 PCLK Peripheral Clock Divider 1 PERI_GR5_CLOCK_CTLregister INT_DIV bit Divider 1 256 LIN C...

Page 10: ...IV bit INT24_DIV bit PERI_CLOCK_CTLregister TYPE_SEL bit DEV_SEL bit 3 dividers 4 dividers 7 dividers 124multiplexers Clock generation Figure 7 Block diagram for the peripheral clock divider 1 Figure 8 shows the distribution of the CLK_HF3 CLK_HF4 CLK_HF5 CLK_HF6 CLK_HF7 CLK_HF8 CLK_HF9 CLK_HF10 CLK_HF11 and CLK_HF12 For details on these functions in Figure 8 see the architecture TRM CLK_HF4 Ether...

Page 11: ...ed on a use case using the sample driver library SDL provided by Infineon The code snippets in this application note are part of the SDL See Other references The SDL has a configuration part and a driver part The configuration part configures the parameter values for the desired operation The driver part configures each register based on the parameter values in the configuration part You can confi...

Page 12: ...arameters section in the TRAVEO T2G user guide for more information Figure 9 shows the ECO setting steps Start Write 1 to ECO_EN Check the state of ECO_OK and the state of TIMEOUT Yes End Success No Define variable to count timeout Configure the initial value of TIMEOUT ECO_OK is already 1 End No change Define TIMEOUT variable Configure TIMEOUT value Write 1 to ECO_EN and to be available ECO TIMEO...

Page 13: ...tting ECO parameters in TRAVEO T2G user guide 7ul CLK_ECO_CONFIG2 ATRIM Amplitude trim Calculated from Setting ECO parameters in TRAVEO T2G user guide 0ul CLK_ECO_CONFIG2 FTRIM Filter trim of 3rd harmonic oscillation Calculated from Setting ECO parameters in TRAVEO T2G user guide 3ul CLK_ECO_CONFIG2 RTRIM Feedback resistor trim Calculated from Setting ECO parameters in TRAVEO T2G user guide 3ul CL...

Page 14: ..._FOR_STABILIZATION Cy_SysLib_DelayUs Wait Time Delay by the specified number of microseconds Wait time 1u 1us 3 1 3 Sample code for initial ECO configuration Code Listing 1 provides a sample code The following description will help you understand the register notation of the driver part of the SDL SRSS unCLK_ECO_CONFIG stcField u1ECO_EN is the SRSS_CLK_ECO_CONFIG ECO_EN mentioned in the Registers ...

Page 15: ...nterrupt __enable_irq Set Clock Configuring registers AllClockConfiguration Please ensure output clock frequency using oscilloscope for Code Listing 2 AllClockConfiguration function static void AllClockConfiguration void ECO setting cy_en_sysclk_status_t ecoStatus ecoStatus Cy_SysClk_EcoConfigureWithMinRneg CLK_FREQ_ECO SUM_LOAD_SHUNT_CAP_IN_PF ESR_IN_OHM MAX_DRIVE_LEVEL_IN_UW MIN_NEG_RESISTANCE C...

Page 16: ...CO_EN 1ul return CY_SYSCLK_INVALID_STATE calculate intermediate values float32_t freqMHz float32_t freq 1000000 0f float32_t maxAmplitude 1000 0f float32_t sqrt float64_t float32_t driveLevel 2 0f float32_t esr M_PI freqMHz float32_t cSum float32_t gm_min 157 91367042f 4 M_PI M_PI 4 minRneg freqMHz freqMHz float32_t cSum float32_t cSum 1000000000 0f Get trim values according to caluculated values ...

Page 17: ...g stcField u2RTRIM rtrim tempTrimEcoCtlReg stcField u3GTRIM gtrim SRSS unCLK_ECO_CONFIG2 u32Register tempTrimEcoCtlReg u32Register SRSS unCLK_ECO_CONFIG stcField u1AGC_EN agcen return CY_SYSCLK_SUCCESS Code Listing 5 Cy_SysClk_SelectEcoAtrim function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoAtrim float32_t maxAmplitude if 0 50f maxAmplitude maxAmplitude 0 55f return 0x04ul else if maxAmplitude ...

Page 18: ...RIM_VALUE Code Listing 7 Cy_SysClk_SelectEcoWDtrim function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoWDtrim float32_t amplitude if 0 50f amplitude amplitude 0 60f return 0x02ul else if amplitude 0 7f return 0x03ul else if amplitude 0 8f return 0x04ul else if amplitude 0 9f return 0x05ul else if amplitude 1 0f return 0x06ul else if amplitude 1 1f return 0x07ul else if 1 1f amplitude return 0x07u...

Page 19: ...e if gm_min 17 6f invalid input return CY_SYSCLK_INVALID_TRIM_VALUE else invalid input return CY_SYSCLK_INVALID_TRIM_VALUE Code Listing 9 Cy_SysClk_SelectEcoRtrim function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoRtrim float32_t freqMHz if freqMHz 28 6f return 0x00ul else if freqMHz 23 33f return 0x01ul else if freqMHz 16 5f return 0x02ul else if freqMHz 0 0f return 0x03ul else invalid input re...

Page 20: ...e variables TIMEOUT Configure TIMEOUT value Write 1 to the WCO_EN bit and make WCO available TIMEOUT 0 Subtract TIMEOUT value End Timeout Yes No Check whether the processing exited the loop at TIMEOUT 1 2 3 4 Figure 10 Enabling WCO 3 2 2 Configuration Table 3 lists the parameters and Table 4 lists the functions of the configuration part of in the SDL for WCO settings Table 3 List of WCO settings p...

Page 21: ...sting 11 to Code Listing 13 show the sample settings Code Listing 11 General configuration of WCO settings Wait time definition define WAIT_FOR_STABILIZATION 10000ul define PLL_400M_0_PATH_NO 1ul define PLL_400M_1_PATH_NO 2ul define PLL_200M_0_PATH_NO 3ul define PLL_200M_1_PATH_NO 4ul static void AllClockConfiguration void int main void disable watchdog timer Cy_WDT_Disable Disable Fll CY_ASSERT C...

Page 22: ...e IMO is enabled so that all functions work properly The IMO will automatically be disabled during DeepSleep Hibernate and XRES modes Therefore it is not required to set the IMO explicitly 3 4 Configuring ILO0 ILO1 The ILO0 is enabled by default Note that the ILO0 is used as the operating clock of the watchdog timer WDT Therefore if the ILO0 is disabled it is necessary to disable the WDT To disabl...

Page 23: ...lection 1 3 Wait until LPECOis available 2 Figure 11 LPECO configuration 3 5 1 Use case Oscillator to use Crystal unit Fundamental frequency 8 MHz Note These values are decided in consultation with the crystal unit vendor Table 5 lists the parameters and Table 6 lists the functions of the configuration part of in the SDL for LPECO settings Table 5 List of LPECO settings parameters Parameters Descr...

Page 24: ...urn the status of LPECO stabilization 3 5 2 Sample code for the initial configuration of LPECO settings Code Listing 14 to Code Listing 20 show the sample code Code Listing 14 General configuration of LPECO settings Wait time definition define WAIT_FOR_STABILIZATION 10000ul define CLK_FREQ_LPECO 8000000ul static void AllClockConfiguration void int main void disable watchdog timer Cy_WDT_Disable En...

Page 25: ...NGE capValue Code Listing 17 Cy_SysClk_ClkBak_LPECO_SetFrequency function __STATIC_INLINE void Cy_SysClk_ClkBak_LPECO_SetFrequency cy_en_clkbak_lpeco_frequency_range_t freqValue BACKUP unLPECO_CTL stcField u1LPECO_FRANGE freqValue Code Listing 18 Cy_SysClk_ClkBak_LPECO_SetAmplitude function __STATIC_INLINE void Cy_SysClk_ClkBak_LPECO_SetAmplitude cy_en_clkbak_lpeco_max_amplitude_t ampValue BACKUP ...

Page 26: ...illator CCO the output frequency of this CCO is controlled by adjusting the trim of the CCO Figure 12 shows the steps to configure the FLL Start End Success Yes Wait until CCOis available Wait until FLL is locked No FLL configuration Enable CCO Enable FLL No Based on the specification of the application configure FLL to each register No FLL already enabled Yes End No Change TIMEOUT Yes No FLL disa...

Page 27: ...CY_SYSCLK_FLLPLL_OUTPUT_AUTO Automatic using the lock indicator CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_OR_ NOTHING Similar to AUTO except that the clock is gated off when unlocked CY_SYSCLK_FLLPLL_OUTPUT_INPUT Select FLL reference input bypass mode CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT Select the FLL output Ignores the lock indicator See SRSS_CLK_FLL_CONFIG3 in the registers TRM for details 0ul Table 8 List of F...

Page 28: ...llStatus CY_SYSCLK_SUCCESS fllStatus CY_SYSCLK_TIMEOUT return Code Listing 23 Cy_SysClk_FllConfigureStandard function cy_en_sysclk_status_t Cy_SysClk_FllConfigureStandard uint32_t inputFreq uint32_t outputFreq cy_en_fll_pll_output_mode_t outputMode check for errors if SRSS unCLK_FLL_CONFIG stcField u1FLL_ENABLE 0ul 1 enabled return CY_SYSCLK_INVALID_STATE else if outputFreq CY_SYSCLK_MIN_FLL_OUTPU...

Page 29: ... CY_SYSCLK_DIV_ROUND uint64_t ccoFreq uint64_t config refDiv uint64_t inputFreq 6 Compute the lock tolerance Recommendation ROUNDUP refDiv fref ccoFreq 3 CCO_Trim_Step 2 config updateTolerance CY_SYSCLK_DIV_ROUNDUP config fllMult 100ul Reciprocal number of Ratio config lockTolerance config updateTolerance 20ul Threshould TODO Need to check the recommend formula to calculate the value 7 Compute the...

Page 30: ...u13FLL_REF_DIV config refDiv tempConfg2 stcField u8LOCK_TOL config lockTolerance tempConfg2 stcField u8UPDATE_TOL config updateTolerance SRSS unCLK_FLL_CONFIG2 u32Register tempConfg2 u32Register update CLK_FLL_CONFIG3 register with 4 parameters un_CLK_FLL_CONFIG3_t tempConfg3 tempConfg3 u32Register SRSS unCLK_FLL_CONFIG3 u32Register tempConfg3 stcField u4FLL_LF_IGAIN config igain tempConfg3 stcFie...

Page 31: ...ld u1FLL_ENABLE 1ul now do the timeout wait for FLL_STATUS bit LOCKED while SRSS unCLK_FLL_STATUS stcField u1LOCKED 0ul if timeoutus 0ul If lock doesn t occur FLL is stopped Cy_SysClk_FllDisable return CY_SYSCLK_TIMEOUT Cy_SysLib_DelayUs 1u timeoutus Lock occurred we need to clear the unlock occurred bit Do so by writing a 1 to it SRSS unCLK_FLL_STATUS stcField u1UNLOCK_OCCURRED 1ul Set the FLL by...

Page 32: ... PLL200M already enabled No Yes End No Change Case PLL400 Case PLL200 PLL400M already enabled No Yes Fractional divider setting Enable fractional divider Use Fractional Divider Yes No SSCG setting Enable SSCG Use SSCG Yes No Yes Wait until PLL400M is locked No Enable PLL400M End Success End Timeout TIMEOUT Yes No End No Change Start Fractional divider settings SSCG settings PLL400M configuration B...

Page 33: ...f the PLL 400 200 of the configuration part of in the SDL for PLL 400 200 settings Table 9 List of PLL 400 settings parameters Parameters Description Value PLL400_0_TARGET_FREQ PLL400 0 target frequency 250 MHz 250000000ul PLL400_1_TARGET_FREQ PLL400 1 target frequency 196 608 MHz 196608000ul WAIT_FOR_STABILIZATION Waiting for stabilization 10000ul PLL400_0_PATH_NO PLL400 0 number 1u PLL400_1_PATH...

Page 34: ... operation PLL400 0 false Enable dithering operation PLL400 1 true pllConfig sscgEn Enable the SSCG PLL400 0 true Enable the SSCG PLL400 1 false pllConfig sscgDitherEn Enable SSCG dithering operation PLL400 0 true Enable SSCG dithering operation PLL400 1 false pllConfig sscgDepth Set the SSCG modulation depth CY_SYSCLK_SSCG_ DEPTH_MINUS_2_0 pllConfig sscgRate Set the SSCG modulation rate CY_SYSCLK...

Page 35: ...LL path number and monitor the PLL configuration PLL400 0 PLL number PLL400_0_PATH_NO Timeout value WAIT_FOR_STABILIZATION Set the PLL path number and monitor the PLL configuration PLL400 1 PLL number PLL400_1_PATH_NO Timeout value WAIT_FOR_STABILIZATION Cy_SysLib_DelayUs Wait Time Delays by the specified number of microseconds Wait time 1u 1us Cy_SysClk_PllManual Configure PLL Number PLL Manual C...

Page 36: ...OURCE_CLOCK_FREQ PATH source clock frequency 16000000ul 16 MHz pllConfig inputFreq Input PLL frequency PATH_SOURCE_CLOCK_ FREQ pllConfig outputFreq Output PLL frequency PLL200 0 PLL200_0_TARGET_FREQ Output PLL frequency PLL200 1 PLL200_1_TARGET_FREQ pllConfig lfMode PLL LF mode 0 VCO frequency is 200 MHz 400 MHz 1 VCO frequency is 170 MHz 200 MHz 0u VCO frequency is 320 MHz pllConfig outputMode Ou...

Page 37: ...k_PllConfigure PLL Number PLL Configure Set the PLL path number and configure the PLL PLL200 0 PLL number PLL200_0_PATH_NO PLL configure g_pll200_0_Config Set the PLL path number and configure the PLL PLL200 1 PLL number PLL200_1_PATH_NO PLL configure g_pll200_1_Config Cy_SysLib_DelayUs Wait Time Delay by the specified number of microseconds Wait time 1u 1us Cy_SysClk_PllManual Configure PLL Numbe...

Page 38: ... 0 PLL400_1_TARGET_FREQ PLL 400 1 PLL200_0_TARGET_FREQ PLL 200 0 PLL200_1_TARGET_FREQ PLL 200 1 PLLlimit g_limPll400MFrac PLL 400 1 only g_limPll400M Other FracBitNum 24ul PLL 400 1 only 0ul Other FeedBackDiv manualConfig feedbackDiv RefDiv manualConfig referenceDiv OutputDiv manualConfig outputDiv FeedBackFracDiv manualConfig fracDiv Cy_SysClk_PllEnable PLL Number Timeout value Set the PLL path n...

Page 39: ..._pll400_0_Config inputFreq PATH_SOURCE_CLOCK_FREQ outputFreq PLL400_0_TARGET_FREQ outputMode CY_SYSCLK_FLLPLL_OUTPUT_AUTO fracEn false fracDitherEn false sscgEn true sscgDitherEn true sscgDepth CY_SYSCLK_SSCG_DEPTH_MINUS_2_0 sscgRate CY_SYSCLK_SSCG_RATE_DIV_512 int main void Enable interrupt __enable_irq Set Clock Configuring registers AllClockConfiguration Please check clock output using oscillos...

Page 40: ...SYSCLK_SUCCESS return status manualConfig outputMode config outputMode manualConfig fracEn config fracEn manualConfig fracDitherEn config fracDitherEn manualConfig sscgEn config sscgEn manualConfig sscgDitherEn config sscgDitherEn manualConfig sscgDepth config sscgDepth manualConfig sscgRate config sscgRate status Cy_SysClk_Pll400MManualConfigure clkPath manualConfig return status Code Listing 29 ...

Page 41: ...Div tempClkPLL400MConfig2Reg stcField u3FRAC_DITHER_EN config fracDitherEn tempClkPLL400MConfig2Reg stcField u1FRAC_EN config fracEn SRSS CLK_PLL400M pllNo unCONFIG2 u32Register tempClkPLL400MConfig2Reg u32Register un_CLK_PLL400M_CONFIG3_t tempClkPLL400MConfig3Reg tempClkPLL400MConfig3Reg u32Register SRSS CLK_PLL400M pllNo unCONFIG3 u32Register tempClkPLL400MConfig3Reg stcField u10SSCG_DEPTH uint3...

Page 42: ...tion for uint32_t i_outDiv lim minOutputDiv i_outDiv lim maxOutputDiv i_outDiv uint64_t tempVco i_outDiv targetOutFreq if tempVco lim minFvco continue else if lim maxFvco tempVco break inFreq refDiv feedBackDiv Fvco feedBackDiv Fvco refDiv inFreq uint64_t tempFeedBackDivLeftShifted tempVco uint64_t fracBitNum uint64_t i_refDiv uint64_t inFreq uint64_t error abs uint64_t targetOutFreq uint64_t frac...

Page 43: ...atus Code Listing 33 General configuration of PLL 200 0 settings define PLL200_0_TARGET_FREQ 160000000ul define PLL200_1_TARGET_FREQ 80000000ul Wait time definition define WAIT_FOR_STABILIZATION 10000ul define PLL_400M_0_PATH_NO 1ul define PLL_400M_1_PATH_NO 2ul define PLL_200M_0_PATH_NO 3ul define PLL_200M_1_PATH_NO 4ul define BYPASSED_PATH_NO 5ul Parameters for Clock Configuration cy_stc_pll_con...

Page 44: ...ul const cy_stc_pll_limitation_t pllLim config lfMode g_limPllLF g_limPllNORM status Cy_SysClk_PllCalucDividers config inputFreq config outputFreq pllLim 0ul Frac bit num manualConfig feedbackDiv manualConfig referenceDiv manualConfig outputDiv NULL if status CY_SYSCLK_SUCCESS return status configure PLL based on calculated values manualConfig lfMode config lfMode manualConfig outputMode config ou...

Page 45: ...Field u5REFERENCE_DIV uint32_t config referenceDiv tempClkPLLConfigReg stcField u5OUTPUT_DIV uint32_t config outputDiv tempClkPLLConfigReg stcField u1PLL_LF_MODE uint32_t config lfMode tempClkPLLConfigReg stcField u2BYPASS_SEL uint32_t config outputMode SRSS unCLK_PLL_CONFIG pllNo u32Register tempClkPLLConfigReg u32Register return CY_SYSCLK_SUCCESS Code Listing 37 Cy_SysClk_GetPllNo function __STA...

Page 46: ...OutputDiv i_outDiv lim maxOutputDiv i_outDiv uint64_t tempVco i_outDiv targetOutFreq if tempVco lim minFvco continue else if lim maxFvco tempVco break inFreq refDiv feedBackDiv Fvco feedBackDiv Fvco refDiv inFreq uint64_t tempFeedBackDivLeftShifted tempVco uint64_t fracBitNum uint64_t i_refDiv uint64_t inFreq uint64_t error abs uint64_t targetOutFreq uint64_t fracBitNum uint64_t inFreq tempFeedBac...

Page 47: ...No cy_en_sysclk_status_t status Cy_SysClk_GetPllNo clkPath pllNo if status CY_SYSCLK_SUCCESS return status first set the PLL enable bit SRSS unCLK_PLL_CONFIG pllNo stcField u1ENABLE 1ul now do the timeout wait for PLL_STATUS bit LOCKED for SRSS unCLK_PLL_STATUS pllNo stcField u1LOCKED 0ul timeoutus 0ul timeoutus Cy_SysLib_DelayUs 1u status timeoutus 0ul CY_SYSCLK_TIMEOUT CY_SYSCLK_SUCCESS return s...

Page 48: ... PATHx Figure 14 shows a generation diagram for CLK_PATH ECO LPECO DSI_MUX PATH_MUX ILO0 ILO1 WCO FLL BYPASS_SEL CLK_PATH0 EXT_CLK BYPASS_SEL CLK_PATH9 CLK_PATH1 2 3 4 5 CLK_PATH6 7 8 IMO ECO LPECO DSI_MUX PATH_MUX ILO0 ILO1 WCO BYPASS_SEL EXT_CLK IMO PLL 0 1 2 3 4 ECO LPECO DSI_MUX PATH_MUX ILO0 ILO1 WCO EXT_CLK IMO ECO LPECO DSI_MUX PATH_MUX ILO0 ILO1 WCO EXT_CLK IMO PLL 5 6 7 Figure 14 Generati...

Page 49: ...T_CLK 2 ECO 4 DSI_MUX 5 LPECO other Reserved Do not use CLK_DSI_SELECT DSI_MUX 4 0 16 ILO0 17 WCO 20 ILO1 Other Reserved Do not use CLK_FLL_CONFIG3 BYPASS_SEL 29 28 0 Default AUTO 1 1 LOCKED_OR_NOTHING 2 2 FLL_REF bypass mode 3 3 FLL_OUT 3 CLK_PLL_CONFIG BYPASS_SEL 29 28 0 Default AUTO 1 1 LOCKED_OR_NOTHING 2 2 PLL_REF bypass mode 3 3 PLL_OUT 3 1 Switching automatically according to the locked sta...

Page 50: ...e following options no division divide by 2 divide by 4 and by 8 Figure 15 shows the details of the ROOT_MUX and predivider ROOT_MUX Predivider CLK_PATH1 CLK_HF0 CLK_HF1 CLK_HF2 CLK_HF3 CLK_HF4 CLK_HF5 CLK_HF6 CLK_HF7 CLK_HF8 CLK_HF9 CLK_HF10 CLK_HF11 CLK_HF12 CLK_HF13 ROOT_DIV CLK_PATH0 CLK_PATH3 CLK_PATH2 CLK_PATH5 CLK_PATH4 CLK_PATH7 CLK_PATH6 CLK_PATH9 CLK_PATH8 Figure 15 ROOT_MUX and predivid...

Page 51: ...ILO0 1 WCO 4 ILO1 5 ECO_Prescaler 6 LPECO_Prescaler other Reserved Do not use 5 4 Configuring CLK_FAST_0 CLK_FAST_1 CLK_FAST_0 and CLK_FAST_1 are generated by dividing CLK_HF1 by x 1 When configuring the CLK_FAST_0 and CLK_FAST_1 configure a value x 0 to 255 divided by the FRAC_DIV bit and INT_DIV bit of the CPUSS_FAST_0_CLOCK_CTL register and CPUSS_FAST_1_CLOCK_CTL register 5 5 Configuring CLK_ME...

Page 52: ...e obtained by dividing CLK_MEM by x 1 After configuring the CLK_MEM configure a value divided x 0 to 255 by the INT_DIV bit of the CPUSS_SLOW_CLOCK_CTL register 5 8 Configuring CLK_GR The clock source of the CLK_GP is the CLK_PERI in groups 3 4 8 and CLK_HF2 in groups 5 6 9 Groups 3 4 8 are clocks divided by CLK_PERI To generate CLK_GR3 CLK_GR4 and CLK_GR8 write the division value from 1 to 255 to...

Page 53: ..._10 X_10 0 1 2 3 PERI_DIV_CMD ENABLE 1 PERI_DIV_CMD DISABLE 1 Configure the number of divisions using Clock Divider 8 0 Disable the peripheral clock divider Select DIV to use Select TYPE to use Select the clock divider to use Configure the number of divisions using Clock Divider 16 0 Configure the number of fractional divisions using Clock Divider 16 5 Configure the number of integer divisions usi...

Page 54: ...ign divider to peripheral Clock Divider 16 0 0 assign to TCPWM0 Group 0 Channel 0 Figure 18 Example procedure for setting the PCLK 5 9 1 2 Configuration Table 17 lists the parameters and Table 18 lists the functions of the configuration part of in the SDL for the PCLK example of the TCPWM timer settings Table 17 List of PCLK example of the TCPWM timer parameters Parameters Description Value PCLK_T...

Page 55: ... 9 2 Sample code for the initial configuration of PCLK settings example of the TCPWM timer Code Listing 40 to Code Listing 43 show the sample code Code Listing 40 General configuration of PCLK example of the TCPWM timer settings define PCLK_TCPWMx_CLOCKSx_COUNTER PCLK_TCPWM0_CLOCKS0 define TCPWM_PERI_CLK_DIVIDER_NO_COUNTER 0u int main void SystemInit __enable_irq Enable global interrupts uint32_t ...

Page 56: ...V_8_BIT else if dividerType CY_SYSCLK_DIV_16_BIT PERI unDIV_16_CTL dividerNum stcField u16INT16_DIV dividerValue else return bad parameter return CY_SYSCLK_BAD_PARAM return CY_SYSCLK_SUCCESS Code Listing 43 Cy_SysClk_PeriphEnableDivider function __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphEnableDivider cy_en_divider_types_t dividerType uint32_t dividerNum specify the divider make the ref...

Page 57: ... prescaler is available No End Yes Configure 8 bit fractional value Configure 10 bit integer value Configure 8 bit fractional value Configure 10 bit integer value ECO prescaler enabled Wait until ECOrescaler is available Note Do not change the ECO_FRAC_DIV and ECO_INT_DIV settings when ECO_DIV_ENABLE 1 Define ECO prescaler target frequency Set ECO prescaler target frequency 1 2 3 Figure 19 Enablin...

Page 58: ...ABILIZATION Waiting for stabilization 10000ul CLK_FREQ_ECO ECO clock frequency 16000000ul 16 MHz PATH_SOURCE_CLOCK_FREQ PATH source clock frequency CLK_FREQ_ECO Table 20 List of ECO prescaler setting functions Functions Description Value AllClockConfiguration Clock configuration Cy_SysClk_SetEco Prescale Inclk Targetclk Set the ECO frequency and target frequency Inclk PATH_SOURCE_CLOCK_FREQ Target...

Page 59: ...ABILIZATION CY_ASSERT ecoPreStatus CY_SYSCLK_SUCCESS return Code Listing 46 Cy_SysClk_SetEcoPrescale function cy_en_sysclk_status_t Cy_SysClk_SetEcoPrescale uint32_t ecoFreq uint32_t targetFreq Frequency of ECO 4MHz 33 33MHz might exceed 32bit value if shifted 8 bit So it uses 64 bit data for fixed point operation Lowest 8 bit are fractional value Next 10 bit are integer value uint64_t fixedPointE...

Page 60: ...tatus if 0ul timeoutus return CY_SYSCLK_TIMEOUT Cy_SysLib_DelayUs 1u timeoutus return CY_SYSCLK_SUCCESS Code Listing 49 Cy_SysClk_GetEcoPrescaleStatus function __STATIC_INLINE cy_en_eco_prescale_enable_t Cy_SysClk_GetEcoPrescaleStatus void return cy_en_eco_prescale_enable_t SRSS unCLK_ECO_PRESCALE stcField u1ECO_DIV_ENABLED If you want to disable the ECO prescaler set the wait time in the same way...

Page 61: ...TRM Start LPECO prescaler enabled Wait until LPECO prescaler is available No End Yes Configure 8 bit fractional value Configure 10 bit integer value Note Do not change the LPECO_FRAC_DIV and LPECO_INT_DIV settings when LPECO_DIV_ENABLE 1 1 2 3 Figure 21 Enabling the LPECO_Prescaler Figure 22 shows the steps to disable the LPECO_Prescaler For details on the LPECO_Prescaler see the architecture TRM ...

Page 62: ...ional divider to generate 32 768 kHz from the LPECO frac fixedPointDivNum 0x000000FFul int fixedPointDivNum 0x0003FF00ul 8ul 1ul Cy_SysClk_ClkBak_LPECO_Ena bleDivider divInt divFract Set the prescaler enable for the LPECO divInt 0x3FF divFract 0xFF Cy_SysClk_ClkBak_LPECO_Pre scalerOkay Return the status from the LPECO after setting the prescaler divider 5 11 3 Sample code for the initial configura...

Page 63: ...ividing number should be larger than 1 0 and smaller than maximum of 10 bit number if fixedPointDivNum64 0x100ull fixedPointDivNum64 0x40000ull return CY_SYSCLK_BAD_PARAM fixedPointDivNum uint32_t fixedPointDivNum64 Cy_SysClk_ClkBak_LPECO_SetPrescaleManual fixedPointDivNum 0x0003FF00ul 8ul 1ul fixedPointDivNum 0x000000FFul return CY_SYSCLK_SUCCESS Code Listing 54 Cy_SysClk_ClkBak_LPECO_SetPrescale...

Page 64: ...return true else return false To disable the LPECO prescaler set the wait time in the same way as the function above and then call the next function Code Listing 57 Cy_SysClk_ClkBak_LPECO_PrescaleDisable function __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkBak_LPECO_PrescaleDisable uint32_t timeoutus Send the disable command BACKUP unLPECO_CTL stcField u1LPECO_EN 0ul Wait for eco prescaler ...

Page 65: ...al function Operation clock clk_sys hclk Channel clock clk_can cclk CAN FD0 CLK_GR5 Group 5 Ch0 PCLK PCLK_CANFD0_CLOCK_CANFD0 Ch1 PCLK PCLK_CANFD0_CLOCK_CANFD1 CAN FD1 Ch0 PCLK PCLK_CANFD1_CLOCK_CANFD0 Ch1 PCLK PCLK_CANFD1_CLOCK_CANFD1 Table 25 Clock input to LIN Peripheral function Operation clock Channel clock clk_lin_ch LIN CLK_GR5 Group 5 Ch0 PCLK PCLK_LIN_CLOCK_CH_EN0 Ch1 PCLK PCLK_LIN_CLOCK_...

Page 66: ...clock calibration counter function The clock calibration counter has two counters that can be used to compare the frequency of two clock sources All clock sources are available as a source for these two clocks For details see the architecture TRM Use the following procedure to calibrate using the clock calibration counter 1 Calibration Counter1 counts clock pulses from Calibration Clock1 the high ...

Page 67: ... ECO clock frequency 16 MHz Reference clock count value 40000ul 6 2 1 2 Configuration Table 31 lists the parameters and Table 32 lists the functions of the configuration part of in the SDL for the clock calibration counter with ILO0 and ECO settings Table 31 List of clock calibration counter with ILO0 and ECO settings parameters Parameters Description Value ILO_0 Define the ILO_0 setting parameter...

Page 68: ...eference clock frequency refClkFreq CLK_FREQ_ECO 6 2 1 3 Sample code for the initial configuration of the clock calibration counter with ILO0 and ECO settings Code Listing 58 to Code Listing 62 show the sample code Code Listing 58 General configuration of the clock calibration counter with ILO0 and ECO settings define CY_SYSCLK_DIV_ROUND a b a b 2ull b define ILO_0 0ul define ILO_1 1ul define ILON...

Page 69: ...cField u1CAL_COUNTER_DONE 0ul 1 done SRSS unCLK_OUTPUT_FAST stcField u4FAST_SEL0 uint32_t clock1 SRSS unCLK_OUTPUT_SLOW stcField u4SLOW_SEL1 uint32_t clock2 SRSS unCLK_OUTPUT_FAST stcField u4FAST_SEL1 7ul slow_sel1 output rtnval CY_SYSCLK_SUCCESS Save this input parameter for use later in other functions No error checking is done on this parameter clk1Count1 count1 Counting starts when counter1 is...

Page 70: ...e field The ILO frequency trim can be updated using the ILOx_FTRIM bit of the CLK_TRIM_ILOx_CTL register The initial value of the ILOx_FTRIM bit is 0x2C Increasing the value of this bit by 0x01 increases the frequency by 1 5 typical decreasing this bit value by 0x01 decreases the frequency by 1 5 typical The CLK_TRIM_ILO0_CTL register is protected by WDT_CTL WDT_LOCK For the specification of the W...

Page 71: ...chdog timer GetILOClockFreq Get the current ILO 0 frequency Cy_SysClk_IloTrim iloFreq iloNo Set the trim iloFreq Current ILO 0 frequency iloFreq iloFreq iloNo Trimming ILO number iloNo ILONo 6 2 2 2 Sample code for the initial configuration of ILO0 calibration using clock calibration counter settings Code Listing 63 to Code Listing 64 show the sample code Code Listing 63 General configuration of I...

Page 72: ...CTL stcField u6ILO1_FTRIM if iloFreq CY_SYSCLK_ILO_TARGET_FREQ iloFreq is too high Reduce the trim value newTrim curTrim CY_SYSCLK_DIV_ROUND iloFreq CY_SYSCLK_ILO_TARGET_FREQ trimStep else iloFreq too low Increase the trim value newTrim curTrim CY_SYSCLK_DIV_ROUND CY_SYSCLK_ILO_TARGET_FREQ iloFreq trimStep Update the trim value if iloNo 0u if WDT unLOCK stcField u2WDT_LOCK 0ul WDT registers are di...

Page 73: ...OT_MUX4 ROOT_MUX5 ROOT_MUX6 ROOT_MUX7 ROOT_MUX3 ROOT_MUX2 ROOT_MUX1 ROOT_MUX0 PATH_MUX8 DSI_MUX8 BYPASS_MUX8 PATH_MUX3 DSI_MUX3 BYPASS_MUX3 PATH_MUX2 DSI_MUX2 BYPASS_MUX2 PATH_MUX1 DSI_MUX1 BYPASS_MUX1 PATH_MUX0 DSI_MUX0 BYPASS_MUX0 LFCLK_SEL CLK_SEL CLK_ILO0 CLK_BAK CLK_HF0 CLK_HF1 CLK_HF2 CLK_HF3 CLK_HF4 CLK_HF5 CLK_HF6 CLK_HF7 LPECO LPECO Prescaler CSV Reset Fault reporting LEGEND 1 Relationshi...

Page 74: ... the CLK_IMO EXT_CLK CLK_ECO or CLK_LPECO CSV_HF6 CSV_HF6 CLK_REF_HF CLK_REF_HF is selected from the CLK_IMO EXT_CLK CLK_ECO or CLK_LPECO CSV_HF7 CLK_HF7 CLK_REF_HF CLK_REF_HF is selected from the CLK_IMO EXT_CLK CLK_ECO or CLK_LPECO CSV_HF8 CLK_HF7 CLK_REF_HF CLK_REF_HF is selected from the CLK_IMO EXT_CLK CLK_ECO or CLK_LPECO CSV_HF9 CLK_HF7 CLK_REF_HF CLK_REF_HF is selected from the CLK_IMO EXT...

Page 75: ...the CM0 and CPUSS slow infrastructure Clock Calibration Counter Clock calibration counter has a function to calibrate the clock using two clocks CSV Clock supervision CXPI Clock extension peripheral interface See the Clock extension peripheral interface CXPI chapter of the TRAVEO T2G architecture TRM for details ECO External crystal oscillator EXT_CLK External clock FLL Frequency locked loop FPU F...

Page 76: ... of the TRAVEO T2G architecture TRM for details SMIF Serial memory interface See the Serial memory interface chapter of the TRAVEO T2G architecture TRM for details TCPWM Timer counter and pulse width modulator See the Timer counter and PWM chapter of the TRAVEO T2G architecture TRM for details VIDEOSS Video subsystem See the Video subsystem chapter of the TRAVEO T2G architecture TRM for details WC...

Page 77: ...eet 32 bit Arm Cortex M7 microcontroller TRAVEO T2G family Doc No 002 24601 CYT3DL datasheet 32 bit Arm Cortex M7 microcontroller TRAVEO T2G family Doc No 002 27763 2 Technical reference manuals Cluster 2D family TRAVEO T2G automotive cluster 2D family architecture technical reference manual TRM Doc No 002 25800 TRAVEO T2G automotive cluster 2D registers technical reference manual TRM for CYT4DN D...

Page 78: ...g startup as sample software to access various peripherals is provided The SDL also serves as a reference to customers for drivers that are not covered by the official AUTOSAR products The SDL cannot be used for production purposes as it does not qualify to any automotive standards The code snippets in this application note are part of the SDL Contact Technical Support to obtain the SDL ...

Page 79: ...019 12 12 New application note A 2021 06 07 Updated to Infineon template B 2021 09 07 Updated Configuration of the Clock Resources Added flowchart and example codes in all instances Updated Configuration of FLL and PLL Added flowchart and example codes in all instances Updated Configuration of the Internal Clock Added flowchart and example codes in all instances Removed Example for Configuring Int...

Page 80: ...tellectual property rights of any third party with respect to any and all information given in this application note The data contained in this document is exclusively intended for technically trained staff It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in thi...

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