Quasi-resonant CoolSET design guide
ICE2QRxx65/80x
Design Guide
22
8 August 2011
7
PCB Layout Recommendation
In power supply system, PCB layout is a key point for a successful design. Following are some suggestions
for this (refer to application circuit in Figure 9).
Minimize the loop with pulse share current or voltage; examples are the loop formed by the bus
voltage source, primary winding, main switch and current sensing resistor or the loop consisting of
secondary winding, output diode and output capacitor, or the loop of VCC power supply.
Good grounding of the CoolSET; as the CoolSET sees every signal to the reference point of the
CoolSET ground which is also the ground of the VCC power supply, it is advisable that the ground of
the CoolSET is connected to the bus voltage ground through a short and thick PCB track in a star
structure. Note that ground of CoolSET is treated as small signal ground and the R
CS
resistor ground
and primary ground of auxiliary winding of the transformer are treasted as power loop ground. It
needs to be separated before connected to the bulk capacitor ground.
Good grounding of other parts/functions. This includes the CoolSET ground, FB loop ground, ZC loop
ground and the VCC loop ground. It is advisable that all the above grounds connected to the
CoolSET ground and then connected to the bus voltage ground using a star-structure.
Power loop grounds can connect to bulk capacitor ground directly and separately; such as EMI filter
return ground Y capacitor, C15, auxiliary winding ground of transformer and the R
CS
resistor.
The high voltage pins are connected to bus voltage in typical applications. During lightning surge test,
the noise on bus voltage is high. It is suggested that the track to high voltage pin shall be kept away
from other small signal tracks. The distance is better to be more than 3mm.
8
Product Portfolio Quasi Resonant CoolSET
®
Type
Package
MOSFET
R
DSon
1
Input power
Input power
Features
2
V
DS
230 V
AC
(85-265) V
AC
ICE2QR0665
DIP-8
650V
3
0.65 Ω
88W
4
50W
4
DFR, PPL
ICE2QR1765
DIP-8
650V
3
1.7 Ω
56W
4
33W
4
DFR, PPL
ICE2QR4765
DIP-8
650V
3
4.7 Ω
30W
4
19W
4
DFR, PPL
ICE2QR0665Z
DIP-7
650V
3
0.65 Ω
79W
4
45W
4
DFR, PPL
ICE2QR1065Z
DIP-7
650V
3
0.92Ω
71.6W
4
41.0W
4
DFR, PPL
ICE2QR1765Z
DIP-7
650V
3
1.7 Ω
54.8W
4
30.6W
4
DFR, PPL
ICE2QR4765Z
DIP-7
650V
3
4.7 Ω
31W
4
18W
4
DFR, PPL
ICE2QR0665G
DSO-12
650V
5
0.65 Ω
79W
6
45W
4
DFR, PPL
ICE2QR1765G
DSO-12
650V
3
1.7 Ω
49W
4
28W
4
DFR, PPL
ICE2QR4765G
DSO-12
650V
3
4.7 Ω
29W
4
17W
4
DFR, PPL
ICE2QR0680Z
DIP-7
800V
0.65 Ω
102W
7
57W
5
DFR, PPL, 800V
ICE2QR2280Z
DIP-7
800V
2.2 Ω
53W
5
30W
5
DFR, PPL, 800V
ICE2QR4780Z
DIP-7
800V
4.7 Ω
39W
5
22W
5
DFR, PPL, 800V
ICE2QR2280G
DSO-12
800V
2.2 Ω
51W
5
30W
5
DFR, PPL, 800V
1
Typical value @ T
j
=25°C
2
DFR=Digital Frequency Reduction; PPL= Peak Power Limitation
3
T
j
=110°C
4
Calculated maximum input power in an open frame design at T
a
=50°C, T
j
=125°C and without copper area heat sink.
5
T
j
=110°C
6
Calculated maximum input power in an open frame design at T
a
=50°C, T
j
=125°C and without copper area heat sink.
7
Calculated maximum input power in an open frame design at T
a
=50°C, T
j
=125°C and with 232mm
2
2 oz copper area heat sink.
