Quasi-resonant CoolSET design guide
ICE2QRxx65/80x
Design Guide
14
8 August 2011
Secondly, as shown in Figure 3, there are two delay times for detection of the zero crossing and turn on of
the MOSFET. The delay time t
Delay1
is the delay from the drain-source voltage cross the bus voltage to the ZC
voltage follows below 100mV. This delay time can be adjusted through changing C
ZC
. The second one, t
Delay2
,
is the delay time from ZC voltage follows below 100mV to the MOSFET is turned on. This second delay time
is determined by CoolSET internal circuit and cannot be changed. Therefore, the capacitance C
ZC
is chosen
to adjust the delay time t
Delay1
MOSFET is justed turned on at the valley point of drain-source voltage. This is
normally done through experiment.
Next, there is a foldback point correction integrated in this pin. This function is to decrease the peak current
limit on current sense pin so that the maximum output power of the converter will not increase when the input
voltage increases. This is done through sensing the current flowing out from ZC pin when MOSFET is turned
on.
When the main power switch is turned on, the negative voltage on auxiliary winding can be calculated as
P
a
BUS
aux
N
N
V
V
(11)
Inside ZC pin, there is a clamping circuit so that the ZC pin voltage is kept at nearly zero. Therefore, the
current flowing out from ZC pin at this moment is
P
ZC
a
BUS
ON
ZC
N
R
N
V
I
1
_
(12)
The threshold in ZC pin to start the foldback point correction is I
ZC
= 0.5 mA. Therefore, R
ZC1
can be chosen
so that
P
a
S
BUS
ZC
N
mA
N
V
R
*
5
.
0
_
1
(13)
In (13), V
BUS_S
is the voltage from which the maximum output power is desired to be maintained at constant
level. The corresponding maximum current sense voltage in relation to the ZC current is shown in Figure 8.
0.6
0.7
0.8
0.9
1
300
500
700
900
1100
1300
1500
1700
1900
2100
Izc(uA)
V
c
s
-m
a
x
(V
)
Figure 8 Maximum current sense limit versus ZC current during MOSFET on-state
In addition, as shown in Figure 3, an overshoot is possible on ZC voltages when MOSFET is turned off. This
is because of the oscillation 1 on drain voltage, shown in Figure 3 may be coupled to the auxiliary winding.
Therefore, the capacitance C
ZC
and ratio can be adjusted to obtain the trade off between the output
overvoltage protection accuracy and the valley switching performace.
If, however, the amplitude of the ring at the ZC pin is too small and the zero crossing cannot be detected, it is
advised to increase the Drian_Source capacitor, C
DS
of the MOSFET. But this capacitor would incur switching
loss, the value is suggested to be as small as possible; best to be <100pF.
Furthermore, to avoid mis-triggerring of ZC detection just after MOSFET is turned off, a ring suppression time
is provided. The ring suppression time is 2.5 μs typically if V
ZC
is higher than 0.7V and it is 25 μs typically if
