TLE5012B
SSC Registers
User’s Manual
78
Rev. 1.2, 2018-02
Note: When an error occurs, the corresponding bit in the safety word remains “0” until the status register is read.
S_WD
1
r
Status Watchdog
Permanent check of watchdog. After watchdog-counter
overflow, the DSPU stops. Deactivation via AS_WD
0
B
normal operation
1
B
watchdog counter expired (DSPU stop), AS_RST
must be activated. Outputs deactivated, pull
up/down active.
Reset: 0
B
S_RST
0
ru
Status Reset
2)
Indication that there has been a reset state.
0
B
no reset since last readout.
1
B
indication of power-up, short power-break, firmware
or active reset. Both normal register and update
buffer will indicate “1” if no prior read-out has been
done (and even if no update pulse has been sent
out).
Reset: 1
B
1) bit remains “1” after error occurred. Bit is cleared to “0” when status register is read via SSC command.
2) bit remains “1” after reset occurred. Bit is cleared to “0” when status register is read via SSC command.
Field
Bits
Type
Description