Infineon Technologies TLE5012B, User Manual, Page: 37 / 105

TLE5012B
Interfaces
User’s Manual 37 Rev. 1.2, 2018-02
5.2.4 Cyclic Redundancy Check (CRC)
A Cyclic Redundancy Check (CRC) is sent in the last 8 bits of the safety word.
•
This CRC is according to the J1850 Bus Specification.
• Every new transfer restarts the CRC generation.
• The Command Word and all Data Words (in any direction) will be taken into account to generate the CRC. The
non-CRC bits -the 8 upper bits- of the safety word).
• Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used
(see
Figure 5-7 )
• The seed value of the fast CRC circuit is ’11111111
B
’.
• The remainder is inverted before transmission.
Figure 5-7 Fast CRC polynomial division circuit
CRC calculation example with SSC interface
In this example the CRC generation for a typical SSC data transfer is shown. In this case the feature Prediction
will be enabled, so the SSC data transfer consists of a command word and a write data word send by the master
(microcrontroller) followed by a safety word -which contains the CRC- send by the slave (TLE5012B).
The command word 5081
H
indicates that a write data word (MSB of the command word at “0”) will follow and that
this data has to be written in the address 08
H
(MOD_2 register). The four LSBs of the command Word indicate
how many 16-bit words will follow (“0001B” in this case).
The write word 0804
H
is sent to enable Prediction , one of the features available with the TLE5012B. The PREDICT
bit (bit 2 of the WRITE Data 1) will be set at “1”.
Note: Before sending a Write Data, it is necessary to receive a Read Data to ensure that the bits that will not be
configurated (changed) are not overwritten with a wrong value (e.g. read-modify-write operation).
After writing the new configuration parameters, the sensor will send a safety word FE89
H
indicating the status
(STAT), the sensor number (RESP, “1110” in this case since there is only one sensor named “00”) and the CRC
(STAT and RESP are not included in its generation). In this case the CRC transmitted is 89
H
.
CRC generation
At the beginning the CRC is set at 00
H
(see Figure 5-9 , line 1). The first step to generate the CRC consists in a
XOR logical operation (line 3) between the 8 MSB bits of the Command Word (line 1) and the seed value 1111111
B
(line 2). Align the generator polynominal (line 4) to the non-zero MSB of the dataset out of the first step (line 3) and
calculate another XOR (line 5).
Figure 5-8 TLE5012B’s CRC generator polynomial for the SSC interface
From this point onwards reiterative XOR logical operations between the data (result of the previous operation) and
the generator polynominal are done till the remaining bits is equal or smaller than 00FF
H
(only 8 bits left). The
xor
X7 X6 X5 X4 X3 X2
xor
X0
xor
xor
Input
Serial
CRC
output
&
TX_CRC
1 1 1 1 1 1 1
1
X1
parallel
Remainder
1
2 3 4 8
+ + + +
x x x x
100011101