42
IM483 Operating Instructions Revision R032306
43
IM483 Operating Instructions Revision R032306
D i r e c t i o n ( P 1 : 3 )
The direction input controls the CW/CCW direction of the motor. The di-
rection of motion will depend upon the wiring of the motor phases. This
input is synchronized to the positive going edge of the step clock input.
E n a b l e ( P 1 : 5 )
This input can be used to enable or disable the driver output circuitry.
When in a logic HIGH (default, unconnected) state the driver outputs
will be enabled and step clock pulses will cause the motor to advance.
When this input is pulled LOW, by means of a switch or sinking output,
the driver output circuitry will be disabled. Please note that the internal
sine/cosine position generator will continue to increment or decrement as
long as step clock pulses are being received by the IM483.
This input is asynchronous to any other input and may be changed at
any time.
R e s e t ( P 1 : 6 )
The reset input will disable the outputs and reset the driver to its initial
state (Phase A OFF, Phase B full ON) when pulled LOW by a switch or
sinking output.
Use of this input may also be used to clear a “Fault” condition, provided
the cause of the fault has been eliminated.
The reset input is asynchronous to any other input and may also be
changed at any time.
I n p u t T i m i n g
The direction input and the microstep resolution inputs are internally
synchronized to the positive going edge of the step clock input. When
the step clock pulse goes HIGH, the state of the direction input and
microstep resolution settings are latched. Any changes made to the direc-
tion and/or microstep resolution will occur on the rising edge of the step
clock pulse following this change. Table 7.4 lists the timing specifications.
g
n
i
m
i
T
t
u
p
n
I
c
i
g
o
L
3
8
4
M
I
n
o
it
a
c
if
i
c
e
p
S
t
u
p
n
I
e
m
i
T
h
t
d
i
W
e
s
l
u
P
m
u
m
i
n
i
M
t
e
s
e
R
S
n
0
0
5
h
t
d
i
W
e
s
l
u
P
m
u
m
i
n
i
M
k
c
o
l
C
p
e
t
S
S
n
5
7
e
m
i
T
n
o
it
u
c
e
x
E
l
a
c
i
p
y
T
k
c
o
l
C
p
e
t
S
S
n
0
0
1
e
m
i
T
n
o
it
u
c
e
x
E
l
a
c
i
p
y
T
n
o
it
u
l
o
s
e
R
p
e
t
s
o
r
c
i
M
o
s
l
A
(
n
o
it
c
e
r
i
D
)
t
c
e
l
e
S
S
n
0
0
1
Table 7.4: Isolated Logic Input Timing