Imagine Selenio 6800 HUC6801+D, Installation And Operation Manual

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HUC6801
+
D
Installation and Operation Manual
17
Copyright © 2010, Harris Corporation
To determine if the HUC6801
+
is in Bypass mode, make the following selection:
Synchronization and Delay
Before upconversion, the SD-SDI input signal is processed by the module’s frame
synchronizer. The frame synchronizer automatically detects and locks to the genlock
reference signal for video timing alignment. The frame synchronizer either drops or repeats
video frames to achieve synchronization.
During upconversion, delay is added to the SDI input signal in the main video processing
path. The amount of delay to the primary signal is dependent upon the type of processing
applied to it.
To compensate for delays from external, upstream processes, you can use the Input Frame
Delay parameter to add processing delay. The Input Frame Delay parameter provides a
delay range between 0 to 6 frames in one-frame increments.
Table 3-3 lists the video propagation delays through the video synchronizer and converter
blocks of the HUC6801
+
.
ArcTransTime AudPr2Gain
ArcHScale AudPr3Gain
ArcVScale AudPr4Gain
ArcHOffset AudPr1Dly
ArcVOffset AudPr2Dly
ArcOverscan AudPr3Dly
ArcSave AudPr4Dly
ArcRecall AudPr12OutGrp
AudPr34OutGrp
Table 3-2 Parameters Disabled in Bypass Mode (Continued)
Disabled Parameters
Setting Description Parameter Navigation
Display Bypass mode status Video Setup Input Bypass Mode
Feedback [
4 , 1 ]
(displays either Off or On )
Table 3-3 Video Propagation Delays for Upconversion
Input Output
Frame
Sync
User-Defined Input
Frame Delay
Upconvert
HD User
Output Delay
SD-525 1080i_59.94 0~1 I-frame 0~6 I-frames 1 I-frame 0~1 I-frame
SD-525 720p_59.94 0~1 I-frame 0~6 I-frames 2 P-frame 0~1 P-frame
SD-625 1080i_50 0~1 I-frame 0~6 I-frames 1 I-frame 0~1 I-frame
SD-625 720p_50 0~1 I-frame 0~6 I-frames 2 P-frame 0~1 P-fame