IEI Technology WAFER-LX3, User Manual

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WAFER-LX3 3.5” Motherboard
Page 27
PCI Version 2.2 compliance
32-bit, 66 MHz PCI bus operation
Target support for fast back-to-back transactions
Arbiter support for three external PCI bus masters
Write gathering and write posting for in-bound write requests
Virtual PCI header support
Delayed transactions for in-bound read requests
Zero wait state operation within a PCI burst
Dynamic clock stop/start support for GLIU and PCI clock domains (this is not
CLKRUN support)
Capable of handling out of bound transactions immediately after reset
2.5.2 PCI Bridge Components
The PCI bus on the WAFER-LX3 is connected to the following components:
2 x Intel® 82551ER PCI Ethernet controllers
1 x ITE IT8888G PCI to ISA bridge
2.5.3 Intel® 82551ER PCI Ethernet Controller
Two Intel® 82551ER PCI Ethernet 10/100BASE-T Ethernet LAN controllers are interfaced
to the AMD Geode™ CS5536 through the PCI bus. The Ethernet controllers are then both
connected to an RJ-45 connector that can be accessed externally. The Intel® 82551ER
controllers and the RJ-45 connectors are shown in Figure 2-12 .