IEI Technology PCIE-9650, User Manual

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PCIE-9650 PICMG 1.3 CPU Card
Page 19
backplane. This enables up to four PCIe x1 or one PCI x4 compatible expansion boards to
be installed on the backplane.
2.5.6 Intel
®
ICH8DO Low Pin Count (LPC) Interface
The ICH8DO LPC interface complies with the LPC 1.1 specifications. The LPC bus from
the ICH8DO is connected to the following components:
BIOS chipset
Super I/O chipset
2.5.7 Intel
®
ICH8DO PCI Interface
The PCI interface on the Intel® ICH8DO is compliant with the PCI Revision 2.3
implementation. Some of the features of the PCI interface are listed below.
PCI Revision 2.3 compliant
33MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to seven PCI bus masters
2.5.8 Intel
®
ICH8DO Real Time Clock
256 bytes of battery backed RAM is provided by the Motorola MC146818A real time clock
(RTC) integrated into the ICH8DO. The RTC operates on a 3V battery and 32.768KHz
crystal. The RTC keeps track of the time and stores system data even when the system is
turned off.
2.5.9 Intel
®
ICH8DO SATA Controller
The two integrated SATA controllers on the ICH8DO southbridge support six SATA II
drives on the PCIE-9650 with independent DMA operations. The SATA controller contains
two modes of operation – a legacy mode using I/O space, and an AHCI mode using
memory space. SATA controller specifications are listed below.
Supports independent DMA operation on up to six ports
Supports six SATA drives