IEI Technology PCIE-9452, User Manual

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PCIE-9452 PICMG 1.3 CPU Card
Page 19
2.6.4 Intel
®
ICH7R Low Pin Count (LPC) Interface
The ICH7R LPC interface complies with the LPC 1.1 specifications. The LPC bus from the
ICH6 is connected to the following components:
BIOS chipset
Super I/O chipset
2.6.5 Intel
®
ICH7R PCI Interface
The PCI interface on the ICH7R is compliant with the PCI Revision 2.3 implementation.
Some of the features of the PCI interface are listed below.
PCI Revision 2.3 compliant
33MHz
5V tolerant PCI signals (except PME#)
Integrated PCI arbiter supports up to seven PCI bus masters
The PCI bus is connected to an interface gold finger on the bottom of the CPU cards and
supports four expansion PCI cards on the backplane.
2.6.6 Intel
®
ICH7R Real Time Clock
256 bytes of battery backed RAM is provided by the Motorola MC146818A real time clock
(RTC) integrated into the ICH6. The RTC operates on a 3V battery and 32.768KHz crystal.
The RTC keeps track of the time and stores system data even when the system is turned
off.
2.6.7 Intel
®
ICH7R SATA Controller
The integrated SATA controller on the ICH7R southbridge supports four SATA drives on
the PCIE-9452 with independent DMA operations. SATA controller specifications are listed
below.
Supports four SATA drives
Supports 3Gb/s data transfer speeds