IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual
2 - 5
July 23, 2009
Notes
Figure 2.3 APWRDIS# Timing
On initial power up APWRDIS# must be held low initially for 8 clocks after PERST# is removed. Then it
must be sampled high 256 clocks after PERSTN# is removed to enable L2 mode. Subsequent PERST# will
not affect the APWRDIS# state. This timing will be provided by the following circuit.
Figure 2.4 APWRDIS# Timing Circuit
Summary of Contents for EB8T5A Eval Board
Page 4: ...IDT Table of Contents EB8T5A Eval Board Manual ii July 23 2009 Notes...
Page 6: ...IDT List of Tables EB8T5A Eval Board Manual iv July 23 2009 Notes...
Page 8: ...IDT List of Figures EB8T5A Eval Board Manual vi July 23 2009 Notes...
Page 12: ...IDT Description of the EB8T5A Eval Board EB8T5A Eval Board Manual 1 4 July 23 2009 Notes...
Page 30: ...IDT Software for the EB8T5A Eval Board EB8T5A Eval Board Manual 3 2 July 23 2009 Notes...
Page 31: ...Notes EB8T5A Eval Board Manual 4 1 July 23 2009 Chapter 4 Schematics Schematics...
