IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual
2 - 8
July 23, 2009
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I
2
C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.
The PES8T5A contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface.
The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all soft-
ware-visible registers. The Master SMBus interface provides connection to the external serial EEPROMs
used for initialization and the I/O expander used for hot-plug signals.
SMBus Slave Interface
On the PES8T5A board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.9.
SWMODE[2:0]
Switch Mode.
These configuration pins determine the PES8T5A switch operating mode.
Default: 0x0
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 through 0x8 - Reserved
REFCLKM
PCI Express Reference Clock Mode Select
. This signal selects the frequency of the ref-
erence clock input.
Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz
MSMBADDR[2:0]
Master SMBus Address.
These pins determine the SMBus address of the serial EEPROM
from which configuration information is loaded.
Default: 0x0
APWRDIS#
Auxiliary Power Disable.
When this pin is active, it disables the device from using auxil-
iary power supply.
Default: 0x0
Signal
Description
Default
S3[4]
CCLKDS
OFF
S3[5]
CCLKUS
OFF
S3[6]
MSMBSMODE
ON
S5[6]
RSTHALT
ON
S5[1]
SWMODE[0]
ON
S5[2]
SWMODE[1]
ON
S5[3]
SWMODE[2]
ON
S5[5]
APWRDIS#
ON
S4[5]
MSMBADDR[1]
ON
S4[6]
MSMBADDR[2]
ON
S4[7]
MSMBADDR[3]
ON
S4[8]
MSMBADDR[4]
ON
Table 2.8 Boot Configuration Vector Switches S3, S4, and S5 (ON=0, OFF=1)
Signal
Description
Table 2.7 Boot Configuration Vector Signals (Part 2 of 2)
Summary of Contents for EB8T5A Eval Board
Page 4: ...IDT Table of Contents EB8T5A Eval Board Manual ii July 23 2009 Notes...
Page 6: ...IDT List of Tables EB8T5A Eval Board Manual iv July 23 2009 Notes...
Page 8: ...IDT List of Figures EB8T5A Eval Board Manual vi July 23 2009 Notes...
Page 12: ...IDT Description of the EB8T5A Eval Board EB8T5A Eval Board Manual 1 4 July 23 2009 Notes...
Page 30: ...IDT Software for the EB8T5A Eval Board EB8T5A Eval Board Manual 3 2 July 23 2009 Notes...
Page 31: ...Notes EB8T5A Eval Board Manual 4 1 July 23 2009 Chapter 4 Schematics Schematics...
